A2 CS - 15 - Hardware and Virtual Machines

CISC

larger instruction set with multiple instruction formats, multi-cycle variable-length instructions requiring more memory, microprogrammable CU, poor pipelineability, more efficient use of RAM, may support microcode

RISC

smaller instruction set with few instruction formats, single-cycle fixed-length instructions requiring less memory, hardwired CU, better pipelineability, heavy use of RAM, uses more general multi-purpose registers

CISC - microprogrammable CU

control signals generated by software: code must be translated into microinstructions to generate so CU operates slower, easy to modify. software is less expensive, able to handle complex instructions

RISC - hardwired CU

control signals generated by hardware: CU can operate faster, difficult to modify. hardware is more expensive, unable to handle complex instructions

interrupt handling with pipelining

kernel consults IDT, links device to ISR, gives address of low level routine to handle interrupt.

either: erases pipeline contents for latest 4 instructions then saves state of remaining process in pipeline on stack to be restored after interrupt is serviced.

or: stores pipeline contents in 5 individual program counter registers to be restored after interrupt is serviced.

interrupts are prioritised using IPL: if interrupt priority > current process then process is suspended, if interrupt priority < current process then interrupt is stored. process with lower IPL is saved in interrupt register to be serviced when IPL falls to that level, current register values stored in PCB

explain pipelining

5 stages in FE cycle, takes 5 clock cycles to complete 1 FE cycle, as an instruction enters stage 2 of FE cycle, processor can already start fetching next instruction

why implement pipelining

allows multiple instructions to be executed simultaneously without waiting until the previous instruction is complete to begin the next, allows more efficient use of resources

5 stages of FE cycle

IF (instruction fetch), ID (decode), OF (operand fetch), IE (execute), WB (result write back)

pipelining issues

RAW, WAW, WAR

read after write

reading from same register that first instruction is writing to, but may read before value is written or ready to read, fix by stalling: identify the error and wait until write is resolved before reading.

write after write

writing to same register, but second instruction writes its result before the first, fix by renaming: modify second instruction to put its result in a different register.

write after read

reading from same register that second instruction is writing to, but second instruction writes its result before first instruction has read it, fix by renaming: modify second instruction to put its result in a different register

name the 4 basic computer architectures

SISD, SIMD, MISD, MIMD

SISD

Single Instruction Single Data, uses single processor, processing one data source, e.g. early personal computers with simple applications

SIMD

Single Instruction Multiple Data, uses single control unit instructing multiple processing units, processing parallel data inputs, e.g. multiple PUs aka array processors found in graphics cards, each pixel can be allocated a PU so brightness adjustments can happen simultaneously to maintain a consistent image

MISD

Multiple Instruction Single Data, many processors, all processing same shared data source, e.g. fault-tolerance system, same data inputted to multiple processors, output only accepted if all outputs are the same

MIMD

Multiple Instruction Multiple Data, many processing units, asynchronously processing parallel data inputs, each processing unit with dedicated cache memory executes a different instruction concurrently, e.g. multi-core systems like supercomputers/massively parallel computers

massively parallel computers

aka supercomputers, linking together several computers with interconnected data pathways, forms one machine with thousands of processors

parallel processing considerations

communication is important as data may need to be passed between processors, software design must consider parallel processing capabilities

parallel processing benefits

faster for processing independent data, removes bottleneck issue with Von Neumann model due to lower latency

parallel processing drawbacks

not suitable for processing dependent data, requires more expensive hardware

virtual machine

emulation of an existing computer system using a host OS and a guest OS for emulation

roles of virtual machines

testing new software on different OS, accessing virus-infected data, running software on OS they weren’t originally intended for, creating OS backups

host OS

the usual OS, controls physical hardware

guest OS

an OS running on a VM, controls virtual hardware

hypervisor

VM software that creates and runs VMs

benefits of VM

can test new software on many different OS emulations as multiple VMs can run simultaneously on same physical computer saves cost of buying lots of different hardware, sandboxed so easier to recover if VM crashes or downloads a virus as host OS is unaffected

drawbacks of VM

some OS cannot be emulated in a VM because they may be new so the VM does not exist yet, performance is slower than real machine because of extra load on host OS

combinational circuit

output depends entirely on input values, e.g. adder circuits

sequential circuit

output depends on input values produced from previous output values, e.g. flip-flop circuits

flip-flop

acts as a single bit of stable memory in storage or RAM with two states, able to maintain stable output Q that can only be changed by either an input pulse or power loss, also generates complement of output Qbar

draw an SR flip-flop circuit

draw a JK flip-flop circuit

Karnaugh maps

method used to simplify logic statements and circuits, uses Gray codes: ordering of binary numbers such that successive numbers differ by only one bit value, e.g. 00 01 11 10

half adder

carries out binary addition on two 1-bit inputs, outputs a sum and a carry bit

full adder

two half adders combined to allow binary addition on two binary number inputs with a carry in, outputs a sum and a carry out

SR flip-flop

set reset flip-flop aka latch, initial state S=0 R=0 → racing state, set state S=1(pulse) R=0 → Q=1 Q’=0, reset state S=0 R=1(pulse) → Q=0 Q’=1, unchanged state S=1 when Q=1 or R=1 when Q=0, invalid state S=1 R=1 → racing state

JK flip-flop

same as SR flip-flop but has clock input, synchronises the two inputs to prevent invalid racing states by toggling after each clock pulse