DSII Exam 2

If we add two numbers of the same sign and the sign of the result is of the opposite sign, did overflow occur?

true

the zero (Z) status bit is 1 if the result is:

0

For 2sC represented numbers, the negative status bit (N) is 1 if the MSbit of the result is:

1

Shift right arithmetic ...

replicates the MSbit to maintain the sign of the operand in 2sC.

A rotate left through carry (RLC) allows us to transfer into the carry the value ..

.. of the MSbit of the operand

Which type of operation is NOT implemented in an ALU?

storage

The ALU outputs the result of ONE and ONLY ONE operation at a time

true

The C and V values are not relevant for (logic or arithmetic)

Logic

A Verilog task is similar to a procedure in a high-level programming language.

true

We can shift or rotate by ONE or MORE positions

true

The VHDL conditional signal assignment is like the procedural if-else, but can be used in the concurrent block of code.

true

The Verilog Conditional Operator can be used in both concurrent and procedural blocks of code.

true

The Verilog conditional operator can be nested.

true

The VHDL select signal assignment is like the procedural case, but can be used in the concurrent block of code

true

Which description results in a more efficient implementation? (structural or behavioral)

structural

The keyword negedge in Verilog detects the occurrence of (falling or rising)

falling edge

The DFF is an (edge or level triggered)

edge triggered device

The user of a memory starts a memory access cycle by first providing the address of the location to be accessed.

true

To write an arbitrary value into a register, we activate which of the following control signals? (reset, cnt up or load)

load

The attribute signal_name'event detects a change in signal name, which can be either low-to-high or high-to-low.

true

Which functional block is responsible for the sequencing of events in the CPU (DP & CU)?

CU

In which functional block is data being processed, i.e. stored, transferred, and manipulated? (DP or CU)

DP

Aside from the IS the ISA contains also information about the organization of storage.

true

The ISA represents the design interface between: options: 1.the logic designer and software designer (programmer). 2. the logic designer and semiconductor manufacturer. 3.the software designer and the user of software products.

the logic designer and software designer (programmer).

In dxpRISC the MAeffective is calculated as the sum of an address offset value and a register value.

true

An ASM Chart binary conditional box has options: one output and two inputs. one input and two outputs.

one input two outputs

Which special function control register that holds the address of the next instruction word (IW) to be fetched? options: PC. IR. SR.

PC

Which special function control register holds the instruction word (IW) of the current instruction? SR. IR. PC.

IR

The Operation Code (OpCode) field in the dxpRISC IW determines options the operation to be performed. ... the values of the status bits.

operation to be performed

An ASM Chart state box captures (sequential or concurrent)

concurrent

To access memory mapped I/O-Ps one uses ... LD and ST instructions. or ... IN and OUT instructions.

LD and ST

A (hardware) stack is a FIFO or LIFO

LIFO

Which of the following are I/O-Ps? MM. PB1 and SW. PM and DM.

PB1 and SW

to access separate mapped I/O-Ps one uses IN and OUT instructions. ... LD and ST instructions.

in and out

Which of the following values are NOT used to calculate the effective memory address for LD and ST? PC. MAoffset - fetched from the PM/MM. Ra.

PC

A JUMP instruction is a control flow instruction which can alter the sequential flow of instruction execution.

true

Which are the two pieces of information that the CU needs to determine what cycle it has to execute? OpCode and current MC. Harvard and von Neumann. Separate and memory mapped I/O-Ps.

OpCode and current MC.

The process during which a binary IW (machine language instruction) is converted into an assembly language instruction is called (assembly or disassembly)

disassmebly

The CST is the design interface between the design of the DP and the CU.

true

Which design tool captures BOTH sequential and concurrent events? (CST or ASM)

ASM

The computer design methodology divides the design into two major functional blocks: DP and CU.

true

Which of the following code representations is NOT (easy) human readable? Assembly language. Machine language. HLPL language.

Machine language.

Which IS or ISA implements only a few tens of instructions and each instruction completes a "simple" operation? CISC. RISC.

RISC.

How many address locations does this address value reference: 1x0x? 4 8 2 1

4

The registers of a register file share ... ... registered files. ... control signals and input and output ports. ... text files.

... control signals and input and output ports.