ITEC 1000 Chapter 8

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24 Terms

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Current CPU Architecture Designs
§ Complex Instruction Set Computers (CISC)

§ Reduced Instruction Set Computers (RISC)
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Current CPU Architectures
§ IBM Mainframe series
§ Intel x86 family
§ IBM POWER/PowerPC family
§ ARM architecture
§ Oracle SPARC family
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Problems with early CPU Architectures
Large number of specialized instructions were rarely
used but added hardware complexity and slowed
down other instructions

§ Slow data memory accesses could be reduced by
increasing the number of general purpose registers

§ Using general registers to hold addresses could reduce the number of addressing modes and simplify
architecture design

§ Fixed-length, fixed-format instruction words would
allow instructions to be fetched and decoded independently and in parallel
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Ways to improve CPU performance
§ Separate Fetch/Execute Units
§ Pipelining
§ Multiple, Parallel Execution Units
§ Scalar Processing
§ Superscalar Processing
§ Branch Instruction Processing
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Fetch Unit
§ Instruction fetch unit
§ Instruction decode unit
p Determine opcode
p Identify type of instruction and
operands

§ Several instructions are fetched in parallel and held in a buffer until decoded and executed

§ Instruction Pointer (IP) register holds instruction
location of current instruction being processed
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Execution Unit
§ Receives instructions from the decoder unit

§ Appropriate execution unit services the instruction
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Instruction Pipelining
Assembly line technique to allow overlapping between fetch-execute cycles of sequences of instructions
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Scalar processing
Average instruction execution is approximately equal to the clock speed of the CPU
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Challenges of Instruction Pipelining
§ Problems from branching
§ Problems from stalling
§ Instructions have different numbers of steps
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Branch Solution
§ Separate pipelines for both possibilities
§ Probabilistic approach
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Stalling Solution
§ Requiring the following instruction to not be dependent on the branch

§ Instruction reordering (superscalar
processing)
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Superscalar Processing
§ Process more than one instruction per clock cycle

§ Separate fetch and execute cycles as much as possible

§ Buffers for fetch and decode phases

§ Parallel execution units
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Out-of-order processing
dependencies
(hazards)
§ Data dependencies
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Control dependencies
flow or branch
dependencies
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Wide Path Memory Access
Retrieve multiple bytes instead of 1 byte at a time
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Memory Interleaving
Partition memory into subsections, each with its own address register and data register
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Cache Line
Unit of transfer between storage and cache memory
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Blocks
are between 8 and 64 bytes
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Tags
pointer to location in main memory
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Cache controller
Hardware that checks tags to determine if in cache
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Hit Ratio
ratio of hits out of total requests
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Two Multiprocessor Configurations
§ Master-slave multiprocessing
§ Symmetrical multiprocessing (SMP)
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Master CPU
§ Manages the system
§ Controls all resources and scheduling
§ Assigns tasks to slave CPUs
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Symmetrical Multiprocessing
§ Each CPU has equal access to resources
§ Each CPU determines what to run using a standard algorithm