NEW A Level Computer Science 1.1

ALU

Arithmetic Logic Unit: Completes all arithmetic and logical operations, such as plus minus, times divide, Boolean TRUE/FALSE, logical gates such as AND, NOT, OR, XOR.

CU

Control Unit, coordinates activities in CPU. Manages flow of data between devices, accepts and decodes instructions.

Registers

Small, high speed memory, which temporarily stores data

Program Counter

Holds address of next instruction to be fetched

Accumulator

Stores results of calculations done by ALU

MAR

Holds address of location of data that is to be read from/written to

MDR

Temporarily holds data that has been read or needs to be written

CIR

Holds current instruction that is being executed, divided into opcode and operand

Opcode

Action CPU must perform

Operand

Data on which operation is executed

Buses

Set of parallel devices that is used to transmit data between two or more connected devices

Data bus

Bi-directional, transfers data between components

Address Bus

Transmits memory addresses between MAR and RAM that specifies the data that is to be sent or retrievedC

Control Bus

Bi-directional, transmits control signals between control unit and internal and external components

Pipelining

Process of completing the FDE cycles of three instructions simultaneously. Reduces the amount of time that the CPU is idle

FDE Cycle

Fetch: Address in PC is copied to MAR. Instruction held at the address in the MAR is transferred from main memory to MDR. Value in MDR copied to CIR.

Decode: Contents of CIR divided into opcode and operand

Execute: Decoded instruction is executed

Clock Speed

Determined by system clock. Generates signals that initiate all activities. More signals, or pulses, means a higher clock speed, so more instructions are executed per second, so faster performance

No. cores

A core is an independent processor capable of fetch-execute cycles. Two cores means that two instructions can be executed at the same time, so more instructions executed per second, increasing performance

Cache

Memory in CPU used for frequently used instructions. Closer than main memory, so the access of data is quicker, speeding up the FDE cycle, and increasing CPU performance

L1 Cache

Small, high-speed memory.

L2 Cache

Medium sized, relatively fast memory

L3 Cache

Large, slower-speed memory

Von Neumann Architecture

Includes basic components of computer and processor in which shared memory and data buses are used. Can be cheaper to develop as control unit is simpler.

Harvard Architecture

Physically separate memories are used for data and instructions. This means the two can be accessed in parallel, allowing quicker execution. Commonly used in embedded systems