18, 19 - Flip Flops & Registers A2

Edge-Triggered D Flip-Flops

Storage elements that change state no more than once during a clock cycle, triggered by the edge of the clock.

M-S D Flip-Flop

A type of flip-flop that includes a Master (M) and Slave (S) latch configuration.

M-stage

The first stage of an M-S D Flip-Flop that changes state while the clock signal is high.

S-stage

The second stage of an M-S D Flip-Flop that changes state when the clock signal is low.

Qm

The output of the M-stage in an M-S D Flip-Flop.

Qs

The output of the S-stage in an M-S D Flip-Flop.

Level-Sensitive

A characteristic of storage elements that respond to input signals as long as the clock signal is active.

Edge-Triggered

An operation mode where flip-flops only change state at specific edges of the clock signal.

Setup Time (tsu)

The minimum time before the clock edge that the D input must be stable.

Hold Time (th)

The minimum time after the clock edge that the D input must remain stable.

Metastability

An unstable condition that can arise if setup or hold time requirements are not met.

Clock-to-Q propagation delay (tcQ)

The time it takes for the output Q to change after a clock edge.

T Flip-Flop

A flip-flop that toggles its state on each positive clock edge when the T input is high.

JK Flip-Flop

A variation of the T Flip-Flop that has two control inputs, J and K.

Gated Latch

A type of latch that has a control signal to determine when it can change state.

Counter Circuit

A circuit that uses flip-flops to count occurrences of an event.

Asynchronous Clear

A clear function for a flip-flop that can be activated regardless of clock state.

Shift Register

A storage device that can shift its stored data left or right with clock signals.

Parallel Access

The ability to transfer all bits of data simultaneously via multiple lines.

Serial Transfer

The method of transferring data one bit at a time over a single line.

Preset Function

An input feature that sets a flip-flop to a specific state upon activation.

Feedback connection

A circuit connection that allows one output to affect its own input.

Master-Slave Configuration

A flip-flop design that uses one latch to store the data while another is updated.

Negative-edge Triggered

A flip-flop that changes its state on the descending edge of the clock signal.

Positive-edge Triggered

A flip-flop that changes its state on the ascending edge of the clock signal.

Basic Shift Register

A shift register that allows shifting of its contents either right or left.