Flip-Flops

Level-Sensitive Latches

Storage elements where the output follows inputs while the clock is active (Clk = 1)

Significance of the Edge-Triggered Elements

Prevents multiple unwanted state changes per cycle by updating state only once per clock cycle.

Built from two gated D latches

Composition of the Master-Slave D Flip-Flop

Master

The gated D latch inside the Master-Slave Flip-Flop that is active when the CLK = 1, and does the job of tracking the D input.

Slave

The gated D latch inside the Master-Slave Flip-Flop that is active when the CLK = 0, and does the job of storing the output given to it by the other gated D latch.

Master latch behavior

• While Clk = 1, the master latch follows the D input.

• But this change is not visible outside.

Slave latch behavior

• The slave latch updates only when Clk switches from 1 → 0.

• It then takes the master’s stored value

Falling edge of the clock.

Inside a default-chosen Master-Slave D Flip-Flop, on the outside view (the visible output) to everyone only changes on what edge of the clock?

Flip-Flop

A storage element that changes state only on the edge of a controlling clock (not while that level is high/low)

Positive-edge flip-flop

The flip-flop where the D input gets responded when Clk goes from 0 to 1.

Negative-edge flip-flop

The flip-flop where the D input gets responded when Clk goes from 1 to 0.

Alternative Edge-Triggered D Flip-Flop

• The flip flop that is implemented by using 6 NAND gates

• Simpler structure than the master-slave flip-flop

• Q updates only on the active clock edge

• After the edge, the circuit ignores further D input changes while Clk = 1

• Provides the same functionality as a master-slave flip flop but with a fewer gates.

Around 8 to 10 gates

No. of gates that are required to make a master-slave latch?

1) Fewer Gates 2) Achieves an edge-triggering without the need of the second latch 3) Fewer transistors are required resulting in lower cost and area 4) Has a shorter propagation paths than cascaded latches

Mention the four reasons that provides us the conclusion of the NAND-Edge triggered flip-flop having a simpler structure than the Master-Slave Flip-Flop.

Clear_n = 0

The active low input that forces the Q to go zero.

Preset_n = 0

The active low input that forces the Q to go one.

Clear_n and Preset_n must not be 0 together.

Warning inside the digital electronics about the active low inputs of the Master-Slave D flip-flop.

Asynchronous Clear/Preset

Outputs on the flip-flop are forced immediately (independent of clock)

Synchronous clear

Outputs on the flip-flop are forced at the next active clock edge.

Clock-to-Q Delay (tcQ)

Time from the clock edge to when the Q output gets updated.

Setup time, hold time, and clock-to-Q delay

Provide all three timing parameters for Flip-Flops.

Metastability

An unstable condition that may occur if setup or hold time requirements are violated.

level-sensitive

Latches are _______________

edge-sensitive

Latches are ______________