Digital Fundamentals - Latches and Flip-Flops

These flashcards cover the key terms and definitions from the lecture notes on digital fundamentals, focusing on latches, flip-flops, and timers.

Latch

A bistable digital circuit used for storing a bit.

Bistable

Having two stable states.

Clock

A triggering input of a flip-flop.

D flip-flop

A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.

J-K flip-flop

A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.

Propagation delay time

The interval of time required after an input signal has been applied for the resulting output signal to change.

Set-up time

The time interval required for the input levels to be on a digital circuit before the clock transition.

Hold time

The time interval required for the input levels to remain steady to a flip-flop after the triggering edge.

Timer

A circuit that can be used as a one-shot or as an oscillator.

S-R latch

The most basic type of latch constructed from NOR or NAND gates.

NOR gate

A digital logic gate that outputs true only when all inputs are false.

NAND gate

A digital logic gate that outputs false only when all inputs are true.

Active-HIGH

A signal condition where higher voltage signifies an active state.

Active-LOW

A signal condition where lower voltage signifies an active state.

Gated latch

A latch that requires an enable input to respond to S and R inputs.

D latch

A latch that combines S and R inputs into a single D input.

Flip-flop

A clocked device where only the clock edge determines state change.

Positive-edge triggered D flip-flop

Sensitive to D input only on the rising edge of the clock.

Negative-edge triggered D flip-flop

Sensitive to D input only on the falling edge of the clock.

J-K flip-flop operation

Changes states when both inputs J and K are high on the active clock edge.

Asynchronous inputs

Inputs that affect the output independent of the clock.

Preset (PRE) input

An asynchronous input that sets the output high, typically active low.

Clear (CLR) input

An asynchronous input that sets the output low, typically active low.

Setup time (ts)

Minimum time before clock edge for stable data.

Hold time (tH)

Minimum time after clock edge for stable data.

Propagation delay (tPLH, tPHL)

Time taken for output to change after clock edge.

Frequency divider

Uses flip-flops to divide input frequency by 2.

Data storage

Using grouped flip-flops connected to parallel data lines.

Monostable multivibrator

A device with only one stable state that returns to a stable state after a trigger.

Retriggerable one-shot

Extends unstable state duration on receiving triggers during its unstable state.

Power failure detection circuit

Uses retriggerable one-shot to detect loss of power through alarms.

555 timer

A versatile timer that can be configured for multiple operations.

Astable multivibrator

A configuration of the 555 timer that produces a continuous square wave.

Duty cycle

The ratio of the time the output is high to the total time period.

Pulse width (tW)

Length of time the one-shot remains in an unstable state.

RC circuit

A circuit composed of resistors and capacitors used for timing applications.

Chart use for frequency

Using a chart to determine frequency based on component values.

Latch

A bistable digital circuit used for storing a bit.

Bistable

Having two stable states.

Clock

A triggering input of a flip-flop.

D flip-flop

A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.

J-K flip-flop

A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.

Propagation delay time

The interval of time required after an input signal has been applied for the resulting output signal to change.

Set-up time

The time interval required for the input levels to be on a digital circuit before the clock transition.

Hold time

The time interval required for the input levels to remain steady to a flip-flop after the triggering edge.

Timer

A circuit that can be used as a one-shot or as an oscillator.

S-R latch

The most basic type of latch constructed from NOR or NAND gates.

NOR gate

A digital logic gate that outputs true only when all inputs are false.

NAND gate

A digital logic gate that outputs false only when all inputs are true.

Active-HIGH

A signal condition where higher voltage signifies an active state.

Active-LOW

A signal condition where lower voltage signifies an active state.

Gated latch

A latch that requires an enable input to respond to S and R inputs.

D latch

A latch that combines S and R inputs into a single D input.

Flip-flop

A clocked device where only the clock edge determines state change.

Positive-edge triggered D flip-flop

Sensitive to D input only on the rising edge of the clock.

Negative-edge triggered D flip-flop

Sensitive to D input only on the falling edge of the clock.

J-K flip-flop operation

Changes states when both inputs J and K are high on the active clock edge.

Asynchronous inputs

Inputs that affect the output independent of the clock.

Preset (PRE) input

An asynchronous input that sets the output high, typically active low.

Clear (CLR) input

An asynchronous input that sets the output low, typically active low.

Setup time (ts)

Minimum time before clock edge for stable data.

Hold time (tH)

Minimum time after clock edge for stable data.

Propagation delay (tPLH, tPHL)

Time taken for output to change after clock edge.

Frequency divider

Uses flip-flops to divide input frequency by 2.

Data storage

Using grouped flip-flops connected to parallel data lines.

Monostable multivibrator

A device with only one stable state that returns to a stable state after a trigger.

Retriggerable one-shot

Extends unstable state duration on receiving triggers during its unstable state.

Power failure detection circuit

Uses retriggerable one-shot to detect loss of power through alarms.

555 timer

A versatile timer that can be configured for multiple operations.

Astable multivibrator

A configuration of the 555 timer that produces a continuous square wave.

Duty cycle

The ratio of the time the output is high to the total time period.

Pulse width (tW)

Length of time the one-shot remains in an unstable state.

RC circuit

A circuit composed of resistors and capacitors used for timing applications.

Chart use for frequency

Using a chart to determine frequency based on component values.

J-K Flip-Flop Operating Modes

1. No Change: When J=0 and K=0, the output Q retains its previous state.
2. Reset: When J=0 and K=1, the output Q is cleared to 0 on the active clock edge.
3. Set: When J=1 and K=0, the output Q is set to 1 on the active clock edge.
4. Toggle: When J=1 and K=1, the output Q inverts its state on the active clock edge.

555 Timer in Monostable Mode

Upon receiving a trigger pulse, the output goes high for a duration determined by an external RC circuit, then returns to its low stable state. It has one stable state and one unstable state.