EE477L MOS VLSI Circuit Design Layout Design

A collection of flashcards covering key vocabulary and concepts from the EE477L MOS VLSI Circuit Design Layout lecture notes.

Digital Design Overview

A flowchart process from concept through testing to layout in circuit design.

Synthesis

The process of compiling a netlist from an HDL (Hardware Description Language) file, such as VHDL or Verilog.

Netlist

A description of which gates are used in a circuit and how they are connected.

Driving Strength

Indicates how many devices a gate can drive, categorized as 1X, 2X, and 4X.

Clock Network Synthesis

The design of a network for the clock signal synchronization in digital circuits.

Partitioning

The process of dividing a chip into smaller blocks to simplify the design and minimize connections.

Floorplanning

Creating functional areas on a chip design, determining where components are placed.

Placement

Nailing down the exact positions of logic gates and I/O drivers within design blocks.

Routing

The process of establishing connections by arranging the wires on a chip after placement.

Lambda Rules

A set of rules in layout design based on the principle that one lambda equals half of the minimum mask dimension.

Parasitics

Unwanted physical components such as capacitance, resistance, and inductance that affect circuit performance.

Capacitance

A parasitic effect resulting from wiring capacitance that can interfere with circuit operation, particularly at high speeds.

RC Time Constant

The delay introduced in a circuit due to resistance (R) and capacitance (C) values.

Behavioral Design

The phase where circuits are defined using a high-level HDL to verify functionality.

Global Routing

The step in routing where resource channels for wires are selected.

Detailed Routing

The step in routing where wires are assigned to specific metal layers and tracks.

VDD and GND Network Synthesis

The organization of power (VDD) and ground (GND) connections in a digital design.