Computer Science-RISC, CISC, pipelining, interrupts and parallel processing

RISC, CISC, pipelining, interrupts and parallel processing

RISC

(reduced instruction set computer) has more focus on processor speed/performance, has more individual instructions which can be optimised via pipelining. Typically, it takes 1 clock cycle per instruction.

CISC

(complex instruction set computer) has more focus on the architecture/hardware. Using this, one can carry out the worth of multiple assembly language instructions in one instruction.

Pipelining

uses a 5-step cycle to carry out instructions in parallel. Consists of:

1. IF (instruction field)

2. ID (instruction decode)

3. OF (operand fetch)

4. IE (instruction execution)

5. WB (writeback result process)

Interrupts

When this occurs, the current program is stopped, processor decides if it is more important or not, if so, it is dealt with before the current program continues.

SISD

(single instruction single data) where the processor handles a single instruction and cannot do it in parallel.

SIMD

(single instruction multiple data) many processors, simultaneous events can happen.

MISD

(multiple instructions single data) handles multiple instructions but not in parallel.

MIMD

(multiple instructions multiple data) can split jobs between processors then combine them, but raw data is better independent. This form is used most often, as well as SIMD.

Von Neumann’s ‘bottleneck’

the small connection like a thin stream between the CU and ALU, which causes a connection limit and leads to latency where ALU does a lot of work and the CU often quickly processes something before lying in disuse for some time.