CSA 2

Main Memory

Main Memory

Holds instructions in sequential locations.

Increment PC

Updates PC to point to next instruction.

Branch or Jump Instruction

Changes the flow of execution to a different address.

Logic Operation

Execute logical functions on data inputs.

Register Z

Temporary storage for ALU results.

Zout

Signal to output data from register Z.

End Signal

Indicates completion of the current instruction cycle.

Hardwired Control Unit

Control unit using fixed logic circuits.

Control Word (CW)

Bits representing various control signals.

T1, T2, ..., Tn

Time slots in control sequence execution.

Processing Unit

Executes machine instructions and coordinates activities.

Instruction Set Processor (ISP)

Another name for the processing unit.

Central Processing Unit (CPU)

Former term for processing unit; now less common.

Fetch Process

Retrieves one instruction at a time.

Branch Instruction

Alters the sequential flow of instruction execution.

Program Counter (PC)

Tracks address of next instruction to execute.

Memory Address Register (MAR)

Holds address for data transfer operations.

Memory Data Register (MDR)

Contains data to be read or written.

Instruction Register (IR)

Holds the instruction currently being executed.

Read Cycle

Process of fetching data from memory.

Write Cycle

Process of storing data into memory.

Data Path

Collective term for registers, ALU, and bus.

Arithmetic Logic Unit (ALU)

Performs arithmetic and logical operations.

Single-bus Organization

Data paths interconnected via a single bus.

Instruction Execution Steps

Includes fetch, increment, and execute phases.

Fetch Phase

Steps to retrieve instruction from memory.

Execution Phase

Carries out actions specified by the instruction.

Control Signals

Direct data transfer and register selection.

Multiplexer (MUX)

Selects input for ALU from registers or constants.

Transparent Registers

Used for temporary storage, not directly referenced.

Operand Fetch

Retrieves data needed for instruction execution.

Result Storage

Saves execution results back to memory.

Program Initialization

Sets PC to first instruction of the program.

Data Transfer Operations

Moving data between registers and ALU.

Instruction Decoder Unit

Generates control signals for instruction execution.

Sequential Execution

Instructions executed in the order they are fetched.

Arithmetic Operation

Perform calculations using processor registers.

Memory Fetch

Retrieve data from a specified memory location.

Data Store

Save data from a register to memory.

Register Transfer

Move data between registers and memory.

Input Gating

Control data loading into registers from bus.

Output Gating

Control data output from registers to bus.

ALU

Performs arithmetic and logic operations.

MAR

Memory Address Register, holds memory addresses.

MDR

Memory Data Register, stores fetched data.

Memory-Function-Complete (MFC)

Signal indicating memory read completion.

Clock Cycle

Basic unit of time for processor operations.

Read Operation

Request to retrieve data from memory.

Write Operation

Request to store data into memory.

R1out

Signal enabling output from register R1.

R4in

Signal enabling input to register R4.

SelectY

Signal to select register Y for ALU input.

R3in

Signal to input data into register R3.

Data Bus

Path for data transfer between components.

Internal Bus

Connects internal processor components.

External Bus

Connects processor to external memory.

Control Lines

Lines that dictate operation of components.

Timing Coordination

Synchronizing operations with device response.

Clock Cycle Duration

Time taken for one complete processor cycle.

MDRinE

Control signal to load data into MDR.

MFC

Memory Function Complete signal indicating data readiness.

MARin

Control signal to load address into MAR.

Read

Command to initiate a memory read operation.

MDRout

Control signal to output data from MDR.

R2in

Control signal to load data into register R2.

Write

Command to initiate a memory write operation.

WMFC

Control signal to wait for MFC signal.

PC

Program Counter, holds address of next instruction.

IR

Instruction Register, stores the current instruction.

Z

Temporary register for storing intermediate results.

Select1

Multiplexer control signal to select input 1.

Offset

Value added to PC for branching instructions.

Branching

Changing the flow of execution to a different instruction.

Condition Codes

Flags indicating the status of the last operation.

Sign Flag

Indicates if the last result was negative.

R1

Register used for storing operands and results.

R3

Register used to hold address for memory read.

Y

Register used to prepare for ALU operations.

Microprogrammed Control

Control signals generated by microprograms.

Control Step Counter

Counter driven by clock for instruction execution.

Status Flags

Signals indicating processor state and control lines.

Decoder-Encoder Block

Circuit generating control outputs from inputs.

Step Decoder

Provides signal lines for control sequence steps.

Microroutine

Sequence of control words for an instruction.

Microinstructions

Individual control words in a microroutine.

Microprogram Memory

Memory storing microroutines for instructions.

Microprogram Counter (μPC)

Counter for reading control words sequentially.

Zin Signal

Enables input to register Z during specific steps.

MFC Signal

Indicates memory function completion.

Control Sequence

Order of control signals for instruction execution.

PCout

Outputs the program counter value.

R1in

Loads data into register R1.

Add

Performs addition operation on registers.

Instruction Execution

Process of carrying out machine instructions.

Control Signals Generation

Process of producing signals for control unit.