CEA201-PT3

How many check bits are needed if the Hamming error correction code is used to detect two bit errors in a 256-bit data word?

a.8 bits

b.9 bits

c.11 bits

d.10 bits

B

To provide for an extremely high data fault tolerance and can sustain multiple simultaneous drive failures, which RAID level applied two different data check algorithms

a.RAID5

b.RAID1

c.RAID0

d.RAID6

D

The______read instruction from its memory location into the processor

a.data operation (do)

b.operand fetch (of)

c.instruction fetch (if)

d.instruction operation decoding (iod)

C

During the execution of a program which gets initialized first?

a.MBR

b.IR

c.MAR

d.PC

D

Which method is used to map logical addresses of variable length onto physical memory?

a.Paging with segmentation

b.Segmentation

c.Overlays

d.Paging

B

Given the bit sequence "10011011", performing a logical right shift by 3 bits will result in _______."

a.11110011

b.00010011

c.10011000

d.11011000

B

The effective address of Register indirect addressing mode is

a.EA = R

b.EA = (R)+A

c.EA = (R)

d.EA = (R)+(A)

C

________ is the standardized scheme for multiple-disk database design.

a.SSD

b.CLV

c.CAV

d.RAID

D

Two processors A and B have clock frequencies of 600 Mhz and 1 Ghz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?

a.Insufficient information

b.A

c.Both take the same time

d.B

C

The registers, ALU and the interconnection between them are collectively called as _____

a.data path

b.process route

c.information path

d.information trail

A

The minimum time delay between two successive memory read operations is ______

a.Delay

b.Latency

c.None of the mentioned

d.Cycle time

D

During the transfer of data between the processor and memory, we use ______

a.TLB

b.Buffers

c.Cache

d.Registers

D

Physical memory is divided into sets of finite size called as ______

a.Frames

b.Pages

c.Vectors

d.Blocks

A

For random memory access, which of the following statement is false?

a.To access to any words or cells in the memory, we need only the their addresses.

b.Addresses consist of rows and columns of addresses

c.Access time to any memory cells or words are the same

d.Data in memory cannot be read or written sequentially by memory address

C

______ is generally used to increase the apparent size of physical memory.

a.Disks

b.Virtual memory

c.Hard-disk

d.Secondary memory

B

The capacitors lose the charge over time due to ________

a.The defect of the capacitor

b.The small current in the transistor after being turned on

c.None of the mentioned

d.The leakage resistance of the capacitor

D

A byte addressable microprocessor has 24 bit address. What is maximum memory capacity?

a.4 MegaByte

b.8 MegaByte

c.32 MegaByte

d.16 MegaByte

D

The disadvantage of DRAM over SRAM is _______

a.Higher heat dissipation

b.All of the mentioned

c.The cells are not static

d.Lower data storage capacities

C

To get the physical address from the logical address generated by CPU we use ____________

a.Overlays

b.MMU

c.MAR

d.TLB

B

The number of bits used to represent various data types is an example of ________ attribute.

a.None of the mentioned

b.Architecture

c.All of the mentioned

d.Organization

B

How many bytes of data does each sector in the hard drive disk have?

a.256

b.1024

c.128

d.512

D

The ________ contains the address of an instruction to be fetched.

a.memory address register

b.program counter

c.instruction register

d.memory buffer register

B

Which statement is correct in memory-mapped I/O?

a.A part of the memory is specifically set aside for the I/O operation

b.The memory and I/O devices have an associated address space

c.The I/O devices and the memory share the same address space

d.The I/O devices have a separate address space

C

For _________ the address field references a main memory address and the referenced register contains a positive displacement from that address.

a.all of the above

b.indexing

c.base-register addressing

d.relative addressing

B

Asumming one magnectic disk has 40 tracks, each track divided into 8 sectors, what is the capacity of this disk?

a.80 KB

b.320 KB

c.640 KB

d.160 KB

D

The main virtue for using single Bus structure is ____________

a.Cost effective connectivity and ease of attaching peripheral devices

b.Cost effective connectivity and speed

c.None of the mentioned

d.Fast data transfers

A

The reason for the cells to lose their state over time is ________

a.Usage of capacitors to store the charge

b.The lower voltage levels

c.Use of Shift registers

d.None of the mentioned

A

______ is generally used to increase the apparent size of physical memory.

a.Secondary memory

b.Hard-disk

c.Disks

d.Virtual memory

D

The smallest entity of memory is called _______

a.Instance

b.Cell

c.Block

d.Unit

B

A typical DRAM has 8 data lines and 11 address lines for both row and column address of the array. The process can be controlled by using row address select (RAS) and column address select (CAS) signals to provide timing to the chip. What is the maximum capacity of this DRAM?

a.8 MBytes

b.None of the mentioned

c.4 MBytes

d.2 MBytes

e.1 MBytes

C

The ________ contains the address of an instruction to be fetched.

a.memory address register

b.instruction register

c.program counter

d.memory buffer register

C

Using Hamming Code with one error corection to store an 12-bit word in memory, the stored word 111001001101 consists of 8 bits data and 4 bit bits parity check. What are the data bits?

a.11100100

b.None of the mentioned

c.00100110

d.01001101

e.11101001

E

______ are numbers and encoded characters, generally used as operands.

a.Input

b.Stored Values

c.Information

d.Data

D

The Reason for the disregarding of the SRAM's is ________

a.Low Efficiency

b.High Cost

c.High power consumption

d.All of the mentioned

B

The chunks of a program, known as pages, could be assigned to available chunks of memory, known as frames, is called __________

a.Paging

b.Segmentation

c.Swapping

d.Virtual Memory

e.Partitioning

A

A processor has 150 different instructions and 50 general purpose registers. A 24-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is:

a.4 bits

b.6 bits

c.5 bits

d.3 bits

A

The _________ controls the movement of data and instructions into and out of the processor.

a.control unit

b.ALU

c.branch

d.shifter

A

Circuits that can hold their state as long as power is applied is _______

a.Static memory

b.Dynamic memory

c.Cache

d.Register

A

The ALU makes use of _______ to store the intermediate results.

a.Accumulators

b.Heap

c.Stack

d.Registers

A

The return address of the Sub-routine is pointed to by _______

a.PC

b.IR

c.Special memory registers

d.MAR

A

The I/O function includes a _______ requirement, to coordinate the flow of traffic between internal resources and external devices

a.erorr corection

b.control and timing

c.processor communication

d.device communication

e.data buffering

B

The advantage of I/O mapped devices to memory mapped is ___________

a.The devices have to deal with fewer address lines

b.The former offers faster transfer of data

c.The devices connected using I/O mapping have a bigger buffer space

d.No advantage as such

A

Indexing performed after the indirection is __________.

a.relative addressing

b.preindexing

c.autoindexing

d.postindexing

D

A memory organisation that can hold upto 1 MByte and has a minimum of 20 address lines, how many data lines can be organized in this chip?

a.4

b.2

c.8

d.1

C

To get the column address of the required data ______ is enabled.

a.Sense/write

b.RAS

c.CAS

d.CS

C

The way in which the components are interrelated is called____.

a.structure

b.organization

c.function

d.architecture

A

What is the DMA method?

a.Direct data exchange between I/O modules and main memory

b.Direct data exchange between external -memory and cache memory

c.Direct data exchange between peripherals and main memory

d.Direct data exchange between main memory and cache memory

A

What is the most common type of external memory in modern computers

a.ROM

b.Optical memory

c.Magnetic memory

d.Flash memory

e.DRAM

D

The decoded instruction is stored in ______

a.IR

b.PC

c.MBR

d.Registers

A

The ________ contains the address of an instruction to be fetched.

a.instruction register

b.memory address register

c.memory buffer register

d.program counter

D