SLR1 - Structure and function of the processor

ALU

Performs arithmetic (add, subtract, multiply, divide) and logic (AND, OR, NOT, comparisons).

Control Unit (CU)

Sends out control signals to coordinate the CPU and other components.

Program Counter (PC)

Holds the memory address of the next instruction to fetch.

Accumulator (ACC)

Stores the results of calculations performed by the ALU.

Memory Address Register (MAR)

Holds the address of the memory location being accessed.

Memory Data Register (MDR)

Holds the data being transferred to or from memory.

Current Instruction Register (CIR)

Holds the instruction currently being decoded and executed.

Buses

Set of parallel wires which connect two or more components inside the CPU.

Data Bus

Transporting data and instructions between components and is bi-directional.

Address Bus

Transfers memory addresses from the CPU to other components.

Control Bus

Transfers control signals (e.g., read, write, clock signals) and is bi-directional.

Fetch

PC transmits signal to MAR; address sent on address bus; instruction fetched into MDR; MDR copied into CIR; PC increments.

Decode

Instruction in CIR is decoded by the Control Unit.

Execute

Instruction is carried out; ALU or CU performs the operation; result stored in ACC or memory.

Clock speed

More cycles per second = faster execution of instructions.

Number of cores

More cores = more instructions processed simultaneously.

Cache size

Larger/faster cache = less time spent accessing slow RAM.

Pipelining

Overlaps fetch, decode, and execute stages to increase CPU efficiency.

Problem with pipelining

Branch (jump) instructions can disrupt the pipeline.

Von Neumann architecture

One memory for both instructions and data; they share the same bus.

Von Neumann bottleneck

Instructions and data cannot be fetched at the same time, slowing performance.

Harvard architecture

Separate memories and buses for instructions and data; faster access.

Use of Harvard architecture

Used in embedded systems like microcontrollers.

Modified Harvard architecture

Modern CPUs use separate caches for instructions and data but share main memory.