CEA201 PT4

The processor needs to store instructions and data temporarily while an instruction is being executed. (T/F)

T

The control unit (CU) does the actual computation or processing of data. (T/F)

F

Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy.

T

Condition codes facilitate multiway branches.

T

The allocation of control information between registers and memory are not considered to be a key design issue.

F

Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.

T

The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline.

T

A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.

F

One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.

T

The predict-never-taken approach is the most popular of all the branch prediction methods.

T

It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.

T

Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.

T

An interrupt is generated from software and it is provoked by the execution of an instruction.

F

While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur.

T

The exception modes have full access to system resources and can change modes freely.

T

__________ are a set of storage locations.

A. Processors

B. PSWs

C. Registers

D. Control units

C

The ________ controls the movement of data and instructions into and out of the processor.

A. control unit

B. ALU

C. shifter

D. branch

A

________ registers may be used only to hold data and cannot be employed in the calculation of an operand address.

A. General purpose

B. Data

C. Address

D. Condition code

B

__________ are bits set by the processor hardware as the result of operations.

A. MIPS

B. Condition codes

C. Stacks

D. PSWs

B

The _________ contains the address of an instruction to be fetched.

A. instruction register

B. memory address register

C. memory buffer register

D. program counter

D

The _________ contains a word of data to be written to memory or the word most recently read.

A. MAR

B. PC

C. MBR

D. IR

C

The ________ determines the opcode and the operand specifiers.

A. decode instruction

B. fetch operands

C. calculate operands

D. execute instruction

A

_________ is a pipeline hazard.

A. Control

B. Resource

C. Data

D. All of the above

D

A ________ hazard occurs when there is a conflict in the access of an operand location.

A. resource

B. data

C. structural

D. control

B

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

A. loop buffer

B. delayed branch

C. multiple stream

D. branch prediction

A

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.

A. dynamic branch

B. loop table

C. branch history table

D. flag

C

The _________ stage includes ALU operations, cache access, and register update.

A. decode

B. execute

C. fetch

D. write back

B

________ is used for debugging.

A. Direction flag

B. Alignment check

C. Trap flag

D. Identification flag

C

The ARM architecture supports _______ execution modes.

A. 2

B. 8

C. 11

D. 7

D

The OS usually runs in ________.

A. supervisor mode

B. abort mode

C. undefined mode

D. fast interrupt mode

A

Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.

(T/F)

T

Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program.

(T/F)

T

The major cost in the life cycle of a system is hardware.

(T/F)

F

It is common for programs, both system and application, to continue to exhibit new bugs after years of operation.

(T/F)

T

Procedure calls and returns are not important aspects of HLL programs.

(T/F)

F

The register file is on the same chip as the ALU and control unit.

(T/F)

T

The register file employs much shorter addresses than addresses for cache and memory.

(T/F)

T

To handle any possible pattern of calls and returns the number of register windows would have to be unbounded.

(T/F)

T

Cache memory is a much faster memory than the register file.

(T/F)

F

The cache is capable of handling global as well as local variables.

(T/F)

T

With simple, one cycle instructions, there is little or no need for microcode.

(T/F)

T

When using graph coloring, nodes that share the same color cannot be assigned to the same register.

(T/F)

F

Almost all RISC instructions use simple register addressing.

(T/F)

T

RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.

(T/F)

T

Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance.(T/F)

T

_________ determines the control and pipeline organization.

A. Calculation

B. Execution sequencing

C. Operations performed

D. Operands used

B

The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture.

A. HLL

B. RISC

C. CISC

D. all of the above

A

_________ is the fastest available storage device.

A. Main memory

B. Cache

C. Register storage

D. HLL

C

The first commercial RISC product was _________.

A. SPARC

B. CISC

C. VAX

D. the Pyramid

D

_________ instructions are used to position quantities in registers temporarily for computational operations.

A. Load-and-store

B. Window

C. Complex

D. Branch

A

Which stage is required for load and store operations?

A. I

B. E

C. D

D. all of the above

D

A ________ instruction can be used to account for data and branch delays.

A. SUB

B. NOOP

C. JUMP

D. all of the above

B

The instruction location immediately following the delayed branch is referred to as the ________.

A. delay load

B. delay file

C. delay slot

D. delay register

C

A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions.

A. delayed load

B. delayed program

C. delayed slot

D. delayed register

A

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU.

A. 16

B. 32

C. 64

D. 128

C

All MIPS R series processor instructions are encoded in a single ________ word format.

A. 4-bit

B. 8-bit

C. 16-bit

D. 32-bit

D

A _________ architecture is one that makes use of more, and more fine-grained pipeline stages.

A. parallel

B. superpipelined

C. superscalar

D. hybrid

B

The R4000 can have as many as _______ instructions in the pipeline at the same time.

A. 8

B. 10

C. 5

D. 3

A

SPARC refers to an architecture defined by ________.

A. Microsoft

B. Apple

C. Sun Microsystems

D. IBM

C

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.

A. write back

B. tag check

C. data cache

D. instruction execute

A

The superscalar approach has now become the standard method for implementing high-performance microprocessors.

(T/F)

T

In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations.

(T/F)

T

In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.

(T/F)

F

The superscalar approach depends on the ability to execute multiple instructions in parallel.

(T/F)

T

True data dependency is also called flow dependency or read after write (RAW) dependency.

(T/F)

T

Resources include: memories, caches, buses, and register-file ports.

(T/F)

T

Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.

(T/F)

F

The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in-order issue) and to write results in that same order (in-order completion).

(T/F)

T

In-order completion requires more complex instruction issue logic than out-of-order completion.

(T/F)

T

The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.

(T/F)

T

Register renaming eliminates antidependencies and output dependencies.

(T/F)

T

In effect, the Pentium 4 architecture implements a CISC instruction set architecture on a RISC microarchitecture.

(T/F)

T

The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution.

(T/F)

T

ARM architecture has yet to implement superscalar techniques in the instruction pipeline.

(T/F)

F

The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems.

(T/F)

T

The superscalar approach can be used on __________ architecture.

A. RISC

B. CISC

C. neither RISC nor CISC

D. both RISC and CISC

D

The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.

A. scalar

B. branch

C. superscalar

D. flow dependency

C

Which of the following is a fundamental limitation to parallelism with which the system must cope?

A. procedural dependency

B. resource conflicts

C. antidependency

D. all of the above

D

The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________.

A. true data dependency

B. output dependency

C. procedural dependency

D. antidependency

A

The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed.

A. resource dependency

B. procedural dependency

C. output dependency

D. true data dependency

B

_______ refers to the process of initiating instruction execution in the processor's functional units.

A. Instruction issue

B. In-order issue

C. Out-of-order issue

D. Procedural issue

A

Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses.

A. in-order issue

B. resource conflict

C. antidependency

D. out-of-order completion

C

________ indicates whether this micro-op is scheduled for execution, has been dispatched for execution, or has completed execution and is ready for retirement.

A. State

B. Memory address

C. Micro-op

D. Alias register

A

__________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.

A. Flow dependency

B. Instruction-level parallelism

C. Machine parallelism

D. Instruction issue

A

_________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.

A. Machine parallelism

B. Instruction-level parallelism

C. Output dependency

D. Procedural dependency

A

________ is a protocol used to issue instructions.

A. Micro-ops

B. Scalar

C. SIMD

D. Instruction issue policy

D

________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles.

A. In-order completion

B. In-order issue

C. Out-of-order completion

D. Out-of-order issue

C

Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?

A. duplication of resources

B. out-of-order issue

C. renaming

D. all of the above

D

The ________ introduced a full-blown superscalar design with out-of-order execution.

A. Pentium

B. Pentium Pro

C. 386

D. 486

B

Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions.

A. 486

B. Pentium

C. Pentium 4

D. Pentium Pro

C

Symmetric multiprocessors (SMPs) are one of the earliest, and still the most common, example of parallel organization.

T

The key to the design of a supercomputer or array processor is to recognize that the main task is to perform arithmetic operations on arrays or vectors of floating-point numbers.

T

The term SMP refers to a computer hardware architecture and also to the operating system behavior that reflects that architecture.

T

With multithreading the instruction stream is divided into several smaller streams, known as threads, such that the threads can be executed in parallel.

T

An attractive feature of an SMP is that the existence of multiple processors is transparent to the user.

T

The main drawback of the bus organization is reliability.

F

An L1 cache that does not connect directly to the bus cannot engage in a snoopy protocol.

T

With a write-update protocol there can be multiple readers but only one writer at a time.

F

The function of switching applications and data resources over from a failed system to an alternative system in the cluster is referred to as failback.

F

The most important measure of performance for a processor is the rate at which it executes instructions.

T