CEA201-PT4

The routine executed in response to an interrupt request is called ________ routine.

a.Sub-routine

b.Serial interrupt

c.Vectored interrupt

d.Interrupt Service

e.Interrupt acknowledge

Interrupt Service

Memory is organized into records and access must be made in a specific linear sequence' is a description of ________

a.sequential access

b.direct access

c.Random access

d.associative

sequential access

Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 32 sectors per track, with 512 bytes each sector. What is the disk capacity?

a.16 GB

b.64 KB

c.32 MB

d.512 KB

e.64 MB

64 MB

The _______ consists of the access time plus any additional time required before a second access can commence.

a.memory cycle time

b.Latency

c.transfer rate

d.direct access

memory cycle time

Using Hamming Code with one error corection to store an 12-bit word in memory, the stored word 001101001110 consists of 8 bits data and 4 bit bits parity check. What are the parity bits?

a.0110

b.0111

c.0101

d.0011

e.None of the mentioned

0110

The _________ scheduler is also known as the dispatcher.

a.I/O

b.short-term

c.medium-term

d.long-term

short-term

Interrupt processing allows an application program to be suspended in order that a variety of conditions can be serviced and later resumed.

a. False

b.True

True

The______defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture

a.ISA

b.HLL

c.API

d.ABI

ABI

When data are moved over longer distances, to or from a remote device, the process is known as____________.

a.data communications

b.data transport (data transfer)

c.registering

d.structuring

data communications

The superscalar approach can be used on __________ architecture.

a.CISC

b.Both CISC and RISC

c.None of the above

d.RISC

Both CISC and RISC

The performance of the cache memory is measured in terms of a quantity called ______

a.Initialization Ratio

b.Instruction Ratio

c.Address Ratio

d.Miss Ratio

e.Hit Ratio

Hit Ratio

Which statement(s) is/are correct about DMA?

a.CPU does not control data transferring

b.CPU controls data transferring

c.It can be done by software

d.It is the fastest method to transfer data between CPU and peripherals

CPU does not control data transferring

Instruction register stores _______

a.Address of the current instruction

b.Data of the current instruction

c.Instruction which is currently executed

d.Address of the next instruction

Instruction which is currently executed

Counters can be designated as__________.

a.neither asynchronous or synchronous

b.both asynchronous and synchronous

c.synchronous

d.asynchronous

both asynchronous and synchronous

The von Neumann architecture is based on which concept?

a.all of the mentioned

b.data and instructions are stored in a single read-write memory

c.execution occurs in a sequential fashion

d.the contents of this memory are addressable by location

all of the mentioned

Which kind of memory management allow(s) the programmer to view memory as consisting of multiple address spaces or segments?

a.Virtual Memory

b.Segmentation

c.Swapping

d.Paging

e.Partitioning

Segmentation

Microprogramming eases the task of designing and implementing the control unit and provide family concept.

a.False

b.True

True

Which properties do all semiconductor memory cells share?

a.they exhibit two stable states which can be used to represent binary 1 and 0

b.they are capable of being written into to set the state

c.they are capable of being read to sense the state

d.all of the mentioned

The correct answer is: all of the mentioned

Which one of the following CPU registers holds the address of the storage location being access

a.IR (Instruction Register)

b.MAR (Memory address register)

c.MBR (Memory Buffer Register)

d.AC (Accumulator)

MAR (Memory address register)

Which of the following attributes belongs to computer organization?

a.Techniques for addressing memory

b.The memory technology used

c.The instruction set

d.I/O mechanism

e.Number of bits used to represent data types

The memory technology used

Consider a 4-drive, 200 GBytes-per-drive RAID array. What is the available data storage capacity for each of the RAID levels 4?

600 GBytes

The sum of the seek time and the rotational delay equals the ______ which is the time it takes to get into position to read or write.

a.gap time

b.access time

c.constant angular velocity

d.transfer time

access time

The ______ determines the opcode and the operand specifiers.
a.calculate operands

b.fetch operands

c.execute instruction

d.decode instruction

d.decode instruction

The _______ is connected to the address lines of the system bus.

a.MAR

b.MBR

c.IR

d.PC

MAR

Computer______refers to those attributes that have a direct impact on the logical execution of a program.

a.architecture

b.design

c.specifics

d.organization

architecture

The effective address of Register addressing mode is

a.EA = R

b.EA = (R)+A

c.EA = (R)

d.EA = (R)+(A)

EA = R

For _________ the address field references a main memory address and the referenced register contains a positive displacement from that address.

a.all of the above

b.base-register addressing

c.indexing

d.relative addressing

indexing

In a_____ binary values are stored using traditional flip-flop logic-gate configurations,

a.RAM

b.SRAM

c.DRAM

d.ROM

SRAM

One distinguishing characteristic of memory that is designated as _________ data from the memory and to write new data into the memory easily and rapidly.

a.RAM

b.ROM

c.EPROM

d.EEPROM

RAM

The most common means of computer/user interaction is a _________

a.keyboard/monitor

b.mouse/printer

c.modem/printer

d.monitor/printer

keyboard/monitor

Assume an instruction set that uses a fixed 14-bit instruction length. Operand specifiers are 6 bits in length. What is the maximum number of one-operand instructions that can be supported?

a.32

b.512

c.64

d.128

e.256

256

Which of the folowing is an example of sequential access media?

a.Magnetic tape

b.Main Memary

c.CD

d.Cache memory

e.Magnetic disk

Magnetic tape

Follow the Amdahl's law for multiprocessors, if only 15% of the code is inherently serial (f = 0.85), running the program on a multicore system with 8 processors, a performance gain (speedup factor) would be ______

a.410%

b.380%

c.400%

d.390%

390%

________ is a principle by which two variables are independent of each other.

a.Completeness

b.Autoindexing

c.Opcode

d.Orthogonality

Orthogonality

The ___________ is a small cache memory associated with the instruction fetch stage of the pipeline.

a.flag

b.loop table

c.dynamic branch

d.branch history table

branch history table

The _________ command causes the I/O module to take an item of data from the data bus a transmit that data item to the peripheral.

a.write

b.read

c.control

d.test

write

Which of the following interrelated factors go into determining the use of the addressing bits?

a.all of the mentioned

b.number of operands

c.number of register sets

d.address range

all of the mentioned

A ________ disk is permanently mounted in the disk drive, such as the hard disk in a pers

a.removable

b.double sided

c.nonremovable

d.movable-head

nonremovable

the technique, that is capable of mimicking the processor and of taking over control of the system from processor, is called ________.

a.Daisy chain

b.Cycle stealing

c.Multiple interrupt lines

d.Bus arbitration

e.Software poll

Cycle stealing

_______ has the advantage of large address space, however it has the disadvantage of references.

a.Immediate addressing

b.Indirect addressing

c.Stack addressing

d.Direct addressing

Indirect addressing

How many check bits are needed if the Hamming error correction code is used to correct one bit error in a 1024-bit data word?

a.11 bits

b.10 bits

c.9 bits

d.8 bíts

11 bits

__________ instructions are used to position quantities in registers temporarily for computational operations.

a.Window

b.Load-and-store

c.Branch

d.Complex

Load-and-store

___________ occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded

a.Deadlock

b.Data hazard

c.Structural hazard

d.Control hazard

e.Structural hazard

Control hazard

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.

a.organizational

b.memory

c.architectural

d.mechanical

architectural

________ are used to designate the source or destination of the data on the data bus

a.control lines

b.system lines

c.data lines

d.address lines

address lines

Architectural attributes include

a.I0 mechanisms

b.control signals

c.memory technology used

d.Interfaces

I0 mechanisms

The instruction location immediately following the delayed branch is referred to as the _______

a.delay file

b.delay load

c.delay register

d.delay slot

delay slot

________ is when the disk rotates more slowly for accesses near the outer edge than for those in center.

a.Constant angular velocity (CAV)

b.Magnetoresistive

c.Seek time

d.Constant linear velocity (CLV)

Constant linear velocity (CLV)

The only form of addressing for branch instructions is _______ addressing.

a.register

b.base

c.relative

d.immediate

immediate

The I/O function includes a _______ requirement, to coordinate the flow of traffic between internal resources and external devices

a.error corection

b.device communication

c.control and timing

d.processor communication

e.data buffering

control and timing