Intel Chapter 2 TERMS (copy)

Real mode memory

Real mode memory

(DOS memory) exists at locations 00000H–FFFFFH, the first 1M byte of the memory system, and is present on all versions of the microprocessor.

Protected mode memory

(Windows memory) exists at any location in the entire protected memory system, but is available only to the 80286–Core2, not to the earlier 8086 or 8088 microprocessors.

Flat mode memory

Windows Vista or Windows 64 is needed to operate the Pentium 4 or Core2 in 64-bit mode using this to access the entire 1T byte of memory.

Thread

consists of a program counter, a register set, and a stack space.

Task

shares with peer threads its code section, data section, and operating system resources

Program Visible

The programming model of the 8086 through the Core2 is considered to be program visible because its registers are used during application programming and are specified by the instructions.

Program Invisible

they are not addressable directly during applications programming, but may be used indirectly during system programming. Only the 80286 and above contain the program-invisible registers.

8-bit registers

are AH, AL, BH, BL, CH, CL, DH, and DL and are referred to when an instruction is formed using these two-letter designations.

16-bit registers

are AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS, CS, DS, ES, SS, FS, and GS. The first 4 16 registers contain a pair of 8-bit registers. An example is AX, which contains AH and AL.

Extended 32 bit registers

are EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI, EIP, and EFLAGS.

Multipurpose registers

include EAX, EBX, ECX, EDX, EBP, EDI, and ESI. These registers hold various data sizes (bytes, words, or doublewords) and are used for almost any purpose, as dictated by a program.

64-bit registers

are designated as RAX, RBX, and so forth.

RAX (accumulator)

is referenced as a 64-bit register, a 32-bit register (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH and AL). The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions. Intel plans to expand the address bus to 52 bits to address 4P (2^52~10^15 =peta) bytes of memory.

RBX (index)

addressable as RBX, EBX, BX, BH, or BL. The BX register sometimes (base index) holds the offset address of a location in the memory system in all versions of the microprocessor.

RCX (count)

addressable as RCX, ECX, CX, CH, or CL, a (count) general-purpose register that also holds the count for various instructions.

RDX (data)

addressable as RDX, EDX, DX, DH, or DL, a (data) general-purpose register holds a part of the result from multiplication or part of dividend before a division.

RBP (base pointer)

addressable as RBP, EBP, or BP, points to a memory (base pointer) location for memory data transfers.

RDI (destination index)

addressable as RDI, EDI, or DI, often addresses (destination index) string destination data for the string instructions.

RSI (source index)

used as RSI, ESI, or SI. – The (source index) register addresses source string data for the string instructions – like RDI, RSI also functions as a generalˇpurpose register.

R8 through 15

These registers are only found in the Pentium 4 and Core2 if 64-bit extensions are enabled. Data in these registers are addressed as 64-, 32-, 16-, or 8 bit sizes and are of general purpose. Most applications will not use these registers until 64-bit processors are common. Note that the 8-bit portion is the rightmost 8-bit only; bits 8 to 15 are not directly addressable as a byte.

SPECIAL PURPOSE REGISTERS

it include RIP, RSP, and RFLAGS; and the segment registers include CS, DS, ES, SS, FS, and GS.

RIP (instruction pointer)

addresses the next instruction in a section of memory defined as (instruction pointer) a code segment.

RSP (stack pointer)

addresses an area of memory called the stack. The stack memory stores data through this pointer. This register is referred to as SP if used as a 16-bit register and ESP if referred to as a 32-bit register.

RFLAGS

indicate the condition of the microprocessor and control its operation. Flags are upward-compatible from the 8086/8088 through Core2. The rightmost five and the overflow flag are changed by most arithmetic and logic operations. Although data transfers do not affect them.

C (carry)

Holds the carry after addition or the borrow after subtraction. The carry flag also indicates error conditions, as dictated by some programs and procedures.

P (parity)

is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even parity.

A (auxiliary carry)

Holds the carry (half-carry) after addition or the borrow after subtraction between bit positions 3 and 4 of the result.

Z (zero)

Shows that the result of an arithmetic or logic operation is zero. If Z = 1, the result is zero; if Z = 0, the result is not zero.

S (sign)

holds the arithmetic sign of the result after an arithmetic or logic instruction executes. If S = 1, the sign bit (leftmost bit of a number) is set or negative; if S =0, the sign bit is cleared or positive

T (trap)

The ____ flag enables trapping through an on-chip debugging feature. (A program is debugged to find an error or bug.) If the T flag is enabled (1), the microprocessor interrupts the flow of the program on conditions as indicated by the debug registers and control registers. If the T flag is a logic 0, the trapping (debugging) feature is disabled. The Visual C++ debugging tool uses the trap feature and debug registers to debug faulty software.

I (interrupt)

The ___flag controls the operation of the INTR (interrupt request) input pin. If I = 1, the INTR pin is enabled; if I = 0, the INTR pin is disabled. The state of the 1 flag bit is controlled by the STI (set I flag) and CLI (clear I flag) instructions.

D (direction)

The ___ flag selects either the increment or decrement mode for the DI and/or SI registers during string instructions. If D = 1, the registers are automatically decremented; if D = 0, the registers are automatically incremented. The D flag is set with the STD (set direction) and cleared with the CLD (clear direction) instructions.

O (overflow)

____ occur when signed numbers are added or subtracted. An ___ indicates that the result has exceeded the capacity of the machine.

IOPL (I/O privilege level)

Is used in protected mode operation to select the privilege level for I/O devices.

NT (nested task)

- The _____ flag indicates that the current task is nested within another task in protected mode operation. This flag is set when the task is nested by software

RF (resume)

The _____ flag is used with debugging to control the resumption of execution after the next instruction.

VM (virtual mode)

The ____ flag bit selects virtual mode operation in a protected mode system. _____ system allows multiple DOS memory partitions that are 1M byte in length to coexist in the memory system.

AC (alignment check)

- The _____ flag bit activates if a word or double word is addressed on a non-word or non-double word boundary.

VIF (virtual interrupt)

The ___ is a copy of the interrupt flag bit available to the Pentium - Pentium 4 microprocessors.

VIP (virtual interrupt pending)

___ provides information about a virtual mode interrupt for the interrupt pending) Pentium–Pentium 4 microprocessors. This is used in multitasking environments to provide the operating system with virtual interrupt flags and interrupt pending information.

ID (identification)

The _____ flag indicates that the Pentium–Pentium 4 microprocessors support the CPUID instruction. The CPUID instruction provides the system with information about the Pentium microprocessor, such as its version number and manufacturer.

SEGMENT REGISTERS

Generate memory addresses when combined with other registers in the microprocessor. There are either four or six segment registers in various versions of the microprocessor. A _____ functions differently in the real mode when compared to the protected mode operation of the microprocessor.

CS (code)

segment holds code (programs and procedures) used by the microprocessor. The _______ register defines the starting address of the section of memory holding code.

DS (data)

The ____ segment is a section of memory that contains most data used by a program. Data are accessed in the data segment by an offset address or the contents of other registers that hold the offset address.

ES (extra)

The ____ segment is an additional data segment that is used by some of the string instructions to hold destination data.

SS (stack)

The ____ segment defines the area of memory used for the stack. The stack entry point is determined by the stack segment and stack pointer registers. The BP register also addresses data within the stack segment.

FS and GS

The ____ segments are supplemental segment registers available in the 80386–Core2 microprocessors to allow two additional memory segments for access by programs. Windows uses these segments for internal operations, but no definition of their usage is available.

Real mode operation

allows the microprocessor to address only the first 1M byte of memory space—even if it is the Pentium 4 or Core2 microprocessor. The first 1M byte of memory is called the real memory, conventional memory, or DOS memory system. All real mode memory addresses must consist of a segment address plus an offset address.

Segment address

defines the beginning address of any 64K-byte memory segment.

Offset address

selects any location within the 64K byte memory segment. Also known as displacement which shows how an offset address.

0H

In the real mode, each segment register is internally appended with this on its rightmost end.

Paragraph

This l6-byte boundary in which real mode segments can begin only at l6-byte boundary in the memory system. EX: if a segment register contains 3000H, the first address of the segment is 30000H, and the last address is or 3FFFFH Segment and offset address are sometimes written as 1000:2000, a segment address of 1000H; an offset of 2000H

microprocessor

has a set of rules that apply to segments whenever memory is addressed which define the segment register and offset register combination.

CS: IP or CS:EIP

combination in which the code segment register is always used with the instruction pointer to address the next instruction in a program.

Code segment register

defines the start of the code segment.

Instruction pointer

locates the next instruction within the code segment.

Stack

another default combination. Stack data are referenced through the stack segment at the memory location addressed by either the stack pointer (SP/ESP) or the pointer (BP/EBP).

Free pointer

Area is indicated by DOS.

Program loader

_______ is handled automatically by this within DOS.

Transient program area (TPA)

it holds the DOS (disk operating system) operating system; other programs that control the computer system

Segment plus offset addressing

allows DOS programs to be relocated in memory.

Relocatable program

is one that can be placed into any area of memory and executed without change.

Relocatable data

are data that can be placed in any area of memory and used without any change to the program.

Protected mode

is where Windows operates. Addressing this extended section of the memory system requires a change to the segment plus an offset addressing scheme used with real mode memory addressing.

Segment register

the ______ contains a selector that selects a descriptor from a descriptor table.

Selector

the segment register contains this that selects a descriptor from a descriptor table.

Descriptor

located in the segment register, and describes the memory segment’s location, length, and access rights of the segment of memory.

Global descriptors (system descriptor)

contain segment definitions that apply to all programs.

Local descriptors (application descriptor)

are usually unique to an application.

Base address

On the descriptor, it indicates the starting location of the memory segment.

G, or granularity bit

allows a segment length of 4K to 4G bytes in steps of 4K bytes.

WIN32

Most Windows applications use a 32-bit environment called.

Access rights byte

controls access to the protected mode segment.

Requested Privilege Level (RPL) .

requests the access privilege level of a memory segment.

Descriptor zero

is called the null descriptor, must contain all zeros, and may not be used for accessing memory.

PROGRAM INVISIBLE REGISTER

The global and local descriptor tables are found in the memory system. In order to access and specify the address of these tables, the 80286–Core2 contain program-invisible registers.

Cache Memory

The program-invisible portion of these registers. Held there and used to access the memory segment until the segment number is changed.

GDTR (global descriptor table register) and IDTR (interrupt descriptor table register)

Contain the base address of the descriptor table and its limit. When protected mode operation desired, address of the global descriptor table and its limit are loaded into the GDTR. The location of the local descriptor table is selected from the global descriptor table. One of the global descriptors is set up to address the local descriptor table

LDTR (local descriptor table register)

is loaded with a selector. Selector accesses global descriptor table, & loads local descriptor table address, limit, & access rights into the cache portion of the___.

Memory paging mechanism

allows any physical memory location to be assigned to any linear address.

Linear address

is defined as the address generated by a program.

Physical address

is the actual memory location accessed by a program.

Page Directory

There is only one in the system. The _contains 1024 double word addresses that locate up to 1024 page tables. The page directory and each page table are 4K bytes in length.

Flat mode memory

is one in which there is no segmentation. First byte address is at 00 0000 0000H; the last location is at FF FFFF FFFFH.