DDCA_Ch4-mine

What are the two leading hardware description languages (HDLs)?

SystemVerilog and VHDL

What does HDL specify?

Logic function only.

What is the purpose of simulation in HDL?

To check outputs for correctness after applying inputs.

What does synthesis do in the context of HDL?

Transforms HDL code into a netlist describing the hardware.

What type of module describes what a module does?

Behavioral module.

What type of module describes how a module is built from simpler modules?

Structural module.

What keyword is used to mark the start and end of a module in SystemVerilog?

module and endmodule.

What operator represents the NOT operation in SystemVerilog?

~ (tilde).

What does the assignment statement 'assign y = a & b;' represent?

An AND operation between a and b.

What does the term 'register' mean in the context of SystemVerilog?

A place to store a value, often used with always_ff.

What does the 'always_comb' statement indicate?

Combinational logic that responds to changes in input signals.

What are the two types of assignment in SystemVerilog?

Blocking (=) and Nonblocking (

What is a key difference between blocking and nonblocking assignment?

Blocking occurs in order, nonblocking occurs simultaneously.

What is the significance of case statements in HDL?

They imply combinational logic and must describe all input combinations.

What does a testbench do in hardware description?

It tests another module by simulating input and checking output.

What command loads a file into an array of testvectors in SystemVerilog?

$readmemb.

What is the purpose of the 'if' statement in sequential logic?

To control flow based on conditions.

What type of signal can be assigned a value of 'z'?

Tristate signal.

What symbol denotes a ternary operator in SystemVerilog?

?: (question mark and colon).

What does 'always_ff @(posedge clk)' signify?

A statement to detect the positive edge of the clock signal.

How is a typical full adder implemented in SystemVerilog?

Using internal nodes for propagate and generate signals.

What is the role of a parameterized module?

To create reusable components with flexible sizes.

What logic level does '4'bz' represent in SystemVerilog?

High impedance (tristate) state.

How do you denote a 3-bit binary number in SystemVerilog?

3'b101.

What error will occur if a name in SystemVerilog starts with a number?

It will result in an invalid name error.

What does 'always_latch' indicate in SystemVerilog?

Potential use of a latch (not recommended in this context).

What function does 'posedge' serve in a clock signal?

It indicates a transition from low to high in a digital signal.

What is meant by a resettable D flip-flop?

A D flip-flop that can reset its output to zero under a reset signal.

What signifies the end of a module in SystemVerilog?

endmodule keyword.

What is a key practice while using articulated state machines?

To ensure proper handling of each state transition.

What specifies that input combinations must include default handling?

Using a default statement in a case construct.

What is the outcome if an expected output does not match the actual output in a testbench?

An error message is displayed, indicating the failure.

What kind of signal can be declared with the keyword 'logic'?

A four-state logic signal allowing 0, 1, x (unknown), and z (high-impedance).

What do you call an operation that combines the outputs of two or more signals?

A logical operation.

How is modular design beneficial in digital circuits?

It encourages reusability of code and easier maintenance.