DDCA_Ch4-mine

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35 Terms

1
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What are the two leading hardware description languages (HDLs)?
SystemVerilog and VHDL
2
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What does HDL specify?
Logic function only.
3
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What is the purpose of simulation in HDL?
To check outputs for correctness after applying inputs.
4
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What does synthesis do in the context of HDL?
Transforms HDL code into a netlist describing the hardware.
5
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What type of module describes what a module does?
Behavioral module.
6
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What type of module describes how a module is built from simpler modules?
Structural module.
7
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What keyword is used to mark the start and end of a module in SystemVerilog?
module and endmodule.
8
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What operator represents the NOT operation in SystemVerilog?
~ (tilde).
9
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What does the assignment statement 'assign y = a & b;' represent?
An AND operation between a and b.
10
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What does the term 'register' mean in the context of SystemVerilog?
A place to store a value, often used with always_ff.
11
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What does the 'always_comb' statement indicate?
Combinational logic that responds to changes in input signals.
12
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What are the two types of assignment in SystemVerilog?
Blocking (=) and Nonblocking (
13
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What is a key difference between blocking and nonblocking assignment?
Blocking occurs in order, nonblocking occurs simultaneously.
14
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What is the significance of case statements in HDL?
They imply combinational logic and must describe all input combinations.
15
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What does a testbench do in hardware description?
It tests another module by simulating input and checking output.
16
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What command loads a file into an array of testvectors in SystemVerilog?
$readmemb.
17
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What is the purpose of the 'if' statement in sequential logic?
To control flow based on conditions.
18
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What type of signal can be assigned a value of 'z'?
Tristate signal.
19
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What symbol denotes a ternary operator in SystemVerilog?
?: (question mark and colon).
20
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What does 'always_ff @(posedge clk)' signify?
A statement to detect the positive edge of the clock signal.
21
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How is a typical full adder implemented in SystemVerilog?
Using internal nodes for propagate and generate signals.
22
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What is the role of a parameterized module?
To create reusable components with flexible sizes.
23
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What logic level does '4'bz' represent in SystemVerilog?
High impedance (tristate) state.
24
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How do you denote a 3-bit binary number in SystemVerilog?
3'b101.
25
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What error will occur if a name in SystemVerilog starts with a number?
It will result in an invalid name error.
26
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What does 'always_latch' indicate in SystemVerilog?
Potential use of a latch (not recommended in this context).
27
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What function does 'posedge' serve in a clock signal?
It indicates a transition from low to high in a digital signal.
28
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What is meant by a resettable D flip-flop?
A D flip-flop that can reset its output to zero under a reset signal.
29
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What signifies the end of a module in SystemVerilog?
endmodule keyword.
30
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What is a key practice while using articulated state machines?
To ensure proper handling of each state transition.
31
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What specifies that input combinations must include default handling?
Using a default statement in a case construct.
32
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What is the outcome if an expected output does not match the actual output in a testbench?
An error message is displayed, indicating the failure.
33
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What kind of signal can be declared with the keyword 'logic'?
A four-state logic signal allowing 0, 1, x (unknown), and z (high-impedance).
34
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What do you call an operation that combines the outputs of two or more signals?
A logical operation.
35
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How is modular design beneficial in digital circuits?
It encourages reusability of code and easier maintenance.