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Memory Latency

The time it takes to access memory; DRAM is slower than the CPU.

SRAM

Faster memory than DRAM but takes more space and gets hotter.

Wide Path Memory Access

Reads or writes multiple bytes at once to speed up data transfer.

Memory Interleaving

Splits memory into sections so different parts can be accessed at the same time.

N-way Interleaving

Divides memory into n parts; even and odd addresses can be accessed at the same time in 2-way interleaving.

Cache Memory

Small, fast memory between the CPU and main memory to speed things up.

Cache Line

A small block of memory in the cache (8-64 bytes).

Tags

Labels in the cache that point to data in the main memory.

Cache Hit

When the data the CPU needs is found in the cache.

Cache Miss

When the data the CPU needs isn’t in the cache and must be loaded from main memory.

Hit Ratio

The percentage of times the CPU finds data in the cache.

Least Recently Used (LRU)

A method to replace old cache data with new data.

Write-Through

Updates both the cache and main memory immediately when data changes.

Write-Back

Updates the main memory later when the cache data is replaced.

Multi-Level Cache

Multiple cache layers (L1, L2, L3) with different speeds and sizes.

Locality of Reference

Most programs access the same small memory area repeatedly, making caching effective.

Shared Cache

A cache shared by multiple CPU cores.