Chapter 9

40-pin

40-pin

8086 and 8088 both are packaged __ in dual in-linepackages (DIPs)

80C88 and 80C86

are CMOS versions that require only 10 mA of power supply cur rent and function in temperature extremes of -40 F through +225 F

noise immunity

is the difference between the logic 0 output voltage and the logic 0 input voltage

LS, 74ALS, or 74HC

The best choice of component types for the connection to an 8086/8088 output pin is an

D-type flip-flop

ensures that the timing requirements of the 8086/8088 RESET input are met

50 με

The flip-flop makes certain that RESET goes high in four clocks, and the RC time constant ensures that it stays high for at least

multiplexed

If the buses are, the address changes at the memory and I/O, which causes them to read or write data in the wrong locations

74LS244

and the control bus signals, MIO, RD, and WR, use a

address, data, and control

The three buses of the 8086 and 8088

bus cycles

The 8086/8088 microprocessors use the memory and I/O in periods called

T1

During the first clocking period in a bus cycle, which is

T2

he 8086/8088 microprocessors issue the RD or WR signal,, and in the case of a write, the data to be written appear on the data bus

T4

all bus signals are deactivated in preparation for the next bus cycle

wait state

A_is an extra clocking period, inserted between T2 and T3 to lengthen the bus cycle.

RDY

is the synchronized ready input to the 8284A clock generator

ASYNC input

The input selects one stage of synchronization when it is a logic 1 and two stages when it is a logic 0

Minimum mode

operation is obtained by connecting the mode selection pin to +5.0 V

maximum mode

is selected by grounding this pin

address/data bus

These pins are at their high-impedance state during a hold acknowledge

address bus

provides the upper-half memory address bits that are present throughout a bus cycle.

address bus

These address connections go to their high impedance state during a hold acknowledge

read signal(rd

is a logic 0, the data bus is receptive to data from the memory or I/O devices connected to the system

read signal(rd

This pin floats to its high-impedance state during a hold acknowledge.

non-maskable interrup(nmi)

input is similar to INTR except that the interrupt does not check to see whether the IF flag bit is a logic 1.

reset

input causes the microprocessor to reset itself if this pin is held high for a minimum of four clocking periods

clock

pin provides the basic timing signal to the microprocessor

bus high enable (bhe

pin is used in the 8086 to enable the most-significant data bus bits (D15-D8) during a read or a write operation

write line

is a strobe that indicates that the 8086/8088 is outputting data to a memory or I/O device

interrupt acknowledge (inta

pin is normally used to gate the interrupt vector number onto the data bus in response to an interrupt request

Address latch enable (ale

This address can be a memory address or an I/O port number. Note that the ALE signal does not float during a hold acknowledge

data transmit/receive (dtr)

This signal is used to enable external data bus buffers

Data bus enable (den

activates external data bus buffers

status bits

indicate the function of the current bus cycle

queue status

bits show the status of the internal instruction queue.

crystal oscillator

pins connect to an external crystal used as the timing source for the clock generator

peripheral clock (pclk

output provides a clock signal to the peripheral equipment in the system

oscillator output (osc)

output provides an EFI input to other 8284A clock generators in some multiple-processor systems

reset input (res)

pin is often connected to an RC network that provides power-on resetting

clock synchronization (CSYNC

pin is used whenever the EFI input provides synchronization in systems with multiple processors

control enable (cen

input enables the command output pins on the 8288

1/0 bus mode (iob

input selects either the I/O bus mode or system bus mode operation

advanced I/O write (AIOWC

is a command output used to provide I/O with an advanced I/O write control signal

master cascade/peripheral data (MCEPDEN

output selects cascade operation for an interrupt controller if IOB is grounded, and enables the I/O bus trans ceivers if IOB is tied high