Pipelining in Processor Architecture

These flashcards cover key terms and concepts related to pipelining in processor architecture, as discussed in the lecture.

Pipelining

An implementation technique where multiple instructions are overlapped in execution, similar to an assembly line.

Throughput

The number of tasks completed in a given time period.

Latency

The time taken from the start to finish for a given task.

Hazards

Situations that prevent starting the next instruction in the subsequent cycle.

Data Hazard

A dependency between instructions where one instruction requires data read/written by a previous one.

Control Hazard

Arises when the decision of the control action depends on a previous instruction.

Forwarding (Bypassing)

A technique to resolve data hazards by using results from previous stages instead of waiting.

Load-Use Data Hazard

Occurs when a load instruction is followed immediately by an instruction that uses the loaded value.

Branch Prediction

Techniques used to predict the outcome of branches to minimize stalling in pipelines.

Register File

A collection of registers used by a CPU to store temporary data.

Instruction Set Architecture (ISA)

Defines the set of instructions that a processor can execute.

Pipeline Stall

A stall initiated to resolve hazards, leading to delays in the execution of instructions.

Instruction Fetch (IF)

The stage where an instruction is read from memory using the PC.

Instruction Decode (ID)

The stage where the fetched instruction is decoded and registers are read.

Execution (EX)

The stage where the operation specified by the instruction is performed.

Memory Access (MEM)

The stage where memory is accessed to read or write data.

Write Back (WB)

The final stage where the result is written back to the register file.