Factors affecting CPU performance

There are three factors that affect CPU performance: clock speed, number of cores and the amount and type of cache memory.

Clock speed

Clock speed

An electronic device which generates signals, switching between 0 and 1. The clock speed is the time taken for one clock cycle to complete. The clock speed is determined by the system clock.

Number of cores

The amount of processing units within a CPU that can operate independently, allowing for multitasking and faster task execution when multiple cores work on the same problem.

Cache memory

A fast, temporary memory built into or close to the CPU to reduce the need to access slower RAM, storing frequently accessed data and instructions for quick retrieval. As cache fills up, unused instructions are replaced.

Von neumann architecture

Includes all the basic components of the computer processor ( single control unit, ALU, registers and memory units) in which a shared data bus is used for both data and instructions. Built on the stored program concept.

Harvard architecture

Has physically seperate memories for instructions and data, more commonly used with embedded processors. Useful for when memories has different characteristics (instructions may be read only, while data may be read-write). This allows you to optimise size of individual memory cells and their buses depending on your needs. (the instruction memory can be designed to be larger so a larger word size can be used for instructions.

Advantages of Von neumann architecture

• Cheaper to develop as the control unit is easier to design

• Programs can be optimised in size

Advantages of harvard architecture

• Quicker execution as data and instructions can be fetched in parallel.

• Memories can be different sizes, which can make more efficient use of space

Contemporary processors

Contemporary processors use a combination of Harvard and Von Neumann architecture. Von Neumann is used when working with data and instructions in main memory, but uses Harvard architecture to divide the cache into instruction cache and data cache.