1.1 The characteristics of contemporary processors, input, output and storage devices

control unit

sends out control signals across the control bus that controls the fetch decode execute cycle

arithmetic logic unit

performs arithmetic and logic operations

program counter

holds memory address location of the next instruction to be executed - once copied to the MAR value is incremented by the incrementor

current instruction register

Holds the current instruction or data being executed, divided into operand and opcode

memory address register

holds the memory location of next instruction or data about to fetched from RAM, points to the location in memory across the address bus

memory data register

temporarily stores data or instructions that have just been fetched from main memory, the instructions are decoded and a copy is placed in the CIR

bus

parallel wires connecting two or more components of a computer

data bus

sends data or instructions between the processor, the memory unit and the input/output devices and is bidirectional

control bus

sends control signals

address bus

sends addresses to memory

explain what happens in fetch stage of the FDE cycle

1. address of next instruction copied from PC to MAR
2. instruction held at that address is copied to MDR - simultaneously contents of PC is incremented so it holds the next address
3. contents of MDR copied to CIR

explain what happens in decode stage of the FDE cycle

1. instruction in CIR is split into opcode and operand
2. address of data is copied to MAR, actual data is copied to MDR or data is passed to ALU

explain what happens in execute stage of the FDE cycle

operand is copied to the MAR, as it provides the address of the data to be loaded, the data at that address is then fetched from RAM and passed up the data bus to the MDR

bus request

indicates a device is requesting use of the data bus

bus grant

Indicates that the CPU has granted access to the data bus.

memory write

Causes data on the data bus to be written into the addressed location.

memory read

Causes data from the addressed location to be placed on the data bus.

interrupt request

Indicates that a device is requesting access to the CPU.

clock

Used to synchronise operations

word size

the number of bits the processor can interpret and execute at a given time

Opcode

The field that denotes the operation and format of an instruction.

operand

the quantity in which an operation is to be done

accumulator

stores results of executions in the ALU

status register

states whether an interrupt request has been received - interrupts would usually be controlled by the operating system and based upon the scheduling algorithms

the speed at which the FDE happens is controlled by the

clock

instruction set

different methods of performing the same instruction, specific to each computer model

factors affecting clock speed

cache size, clock speed, number of cores

pipelining

allows overlapping execution if multiple instructions

Von Neumann Architecture negatives

Data and instructions both use data bus but can only do either data or instructions at a time so causes bottleneck

Harvard architecture advantages

separate memory for data and programs, dedicated buses, data and instructions can be fetched simultaneously, no bottleneck occurs

Harvard Architecture Disadvantages

More expensive as you have to make two separate RAMs
Less RAM accessible overall
Complex to implement

Modern CPU architecture