CS - System Architecture 1

Address

Unique identifier for each memory location.

Architecture

Describes processor content and layout.

FDE Cycle

Fetch-Decode-Execute cycle for task execution.

Central Processing Unit (CPU)

Processes data and carries out instructions.

Von-Neumann Architecture

Stores instructions and data in the same memory.

Registers

High-speed storage locations in the CPU.

Memory Address Register (MAR)

Stores address of accessed data/instruction.

Memory Data Register (MDR)

Temporarily holds data/instruction from RAM.

Program Counter (PC)

Holds address of the next instruction.

Accumulator (ACC)

Stores immediate results from ALU calculations.

Current Instruction Register (CIR)

Splits instruction into opcode and operand.

Arithmetic Logic Unit (ALU)

Performs arithmetic and logical operations.

Buses

Transport data, addresses, and control signals.

Control Unit (CU)

Manages data movement and controls hardware.

Cache

Fast memory storing frequently used data.

Clock Speed

Number of instructions processed per second.

Number of Cores

Independent processing units within a CPU.

Cache Size

Larger size allows faster data retrieval.

Embedded Systems

Computer systems in larger devices for specific tasks.

Examples of Embedded Systems

Washing machines, microwaves, smart fridges.

Fetch Phase

PC contents transferred to MAR, increments by 1.

Decode Phase

Instruction transferred to MDR, decoded in CIR.

Execute Phase

Instruction split into opcode and operand.