Final Exam 341

A computer in an Amazon building accessed by thousands of people for online shopping.
a. Embedded
b. Server
c. PC

server

A given application written in Java runs 15 seconds on a desktop processor. A new Java compiler is
released that requires only 0.6 as many instructions as the old compiler. Unfortunately, it increases the
CPI by 1.1. How fast can we expect the application to run using this new compiler?
a. 15x 0.6 /1.1 = 8.2 sec 3
b. 15 x 0.6 x 1.1 = 9.9 sec
c. 15 x 1.1 / 0.6 = 27.5 sec

15 x 0.6 x 1.1 = 9.9 sec

Indicate whether addi $s1, $s3, 20 is a valid MIPS instruction.
a. True
b. False

true

A megabyte is one Byte

million

"Bit" is short for "binary digit."
a. True
b. False

true

Operating system and compiler are central to every computer system.
a. True
b. False

true

The number 12 can be represented in binary as 1100. If a computer's memory location contains
00001100, then that location contains the number 12.
a. True
b. False

false

The corresponding binary representation of number DB in hexadecimal is ___.
a. 10101110
b. 11011011
c. 01011100
d. 10111100

11011011

The following could be an assembly language instruction: 1000110010100000.
a. True
b. False

false

Computer A: 2GHz, 10s CPU time. In order to design a computer B with 6s CPU time and 1.2 times
clock cycles (CPI) of computer A assuming both use the same amount of instruction count, how fast
must computer B clock be?
a. 2 GHz
b. 4 GHz
c. 6 GHz
d. 8 GHz
e. None

4 GHz

Replacing a processor in a computer with a faster processor has what effect?
a. Decreases response time
b. Increases throughput
c. Both (decreases response time and increases throughput)

Both

Instructions, as well as data, can be stored in memory as numbers.
a. True
b. False

True

The alignment restriction refers to that words must start at addresses that are multiple of 4 in MIPS
a. True
b. False

true

rt is always referred as the second source register for MIPS instruction.
a. True
b. False

false

Indicate whether name $one refers to a MIPS register
a. True
b. False

false

Indicate whether lw $s1, 20($s8) is a valid MIPS instruction.

true or false

false

More registers may benefit an assembly program, but may directly lead to a _____ clock frequency.
a. Faster
b. Same
c. Slower
d. Broken

slower

Consider the 32-bit binary number 11100000 11000000 00000000 00000001, stored in the word with address 5000. For a big-endian architecture, what value is stored in byte 5002?
a. 11100000
b. 00000000
c. 00000001
d. 11000000

00000000

Consider the 32-bit binary number 11100000 11000000 00000000 00000001, stored in the word with address 5000. For a little-endian architecture, what value is stored in byte 5001?
a. 11100000
b. 00000000
c. 00000001
d. 11000000

00000000

If $s3 has 900, $t0 has 77, and memory locations 900, 904, and 908 have 10, 15, 20 respectively, what does location 900 have after the following instruction? sw $t0, 8($s3)
a. 10
b. 15
c. 20
d. 77

10

If $s3 has 900, $t0 has 77, and memory locations 900, 904, and 908 have 10, 15, 20 respectively, what does location 908 have after the following instruction? sw $t0, 8($s3)
a. 10
b. 15
c. 20
d. 77

77

In two's complement, is the following number positive or negative? 1111 0000 0000 0000 0000 0000 0000 0000
a. Positive
b. Negative

negative

Indicate if the binary operation (two's complement representation) resulted in overflow.

0111 0000 0000 0000 0000 0000 0000 0000

+ 1111 0000 0000 0000 0000 0000 0000 0000
a. Overflow
b. No overflow

no overflow

Opcode 0 and a funct field of 34 indicates a(n) _____ instruction.
a. Add immediate
b. Add
c. Sub
d. Logic AND

sub

Opcode 35 indicates a(n) _ _ _ _ instruction

lw

Consider the subtraction of base ten numbers 6 - 4 using 32-bit binary numbers, and achieved by adding 6 with the two's complement of 4. What is the value of zyxw?
a. 1011
b. 1100
c. 1010
d. 0010

0010

instructions can be represented as bits

True or false

true

A multiplexor is also called a selector, where its output is one of the inputs that is selected by a control.
a. True
b. False

true

A register is a _____ element.
a. Combinational
b. State

state

An edge-triggered clocking methodology means that any values stored in a sequential logic element are updated on a clock edge either from low to high or vice versa.
a. True
b. False

true

A rising clock edge refers to the clock changing from _____.
a. 0 to 1
b. 1 to 0
c. Either 0 to 1, or 1 to 0

0 to 1

Consider a rising clock edge that cause 5000 to be written into the PC. After the address 5000 is read into the PC, the 5000 only propagates to the adder.

true or false

false

The design of register file can read from two registers and write to one register during the same clock cycle.
a. True
b. False

true

A register write must be explicitly indicated by asserting the write control signal.
a. True
b. False

true

For R-type instruction with three register operands, we need to read data(s) word from the register file.
a. One
b. Two
c. Three

two

An sign-extend is used to increase the size of a data item by replicating the high order sign bit of the original data item in the high order bits of the larger, destination data item

true or false

true

In addition to the register file and ALU, a branch instruction doesn’t involve

a. PC

b. sign extension

c. shift left

d. data memory

data memory

For R-type instruction with three register operands, we will need a total of___ outputs for the register file.
a. One
b. Two

two

For the store instruction sw $t1, offset_value($t2), the value to be stored must also be read from the register file where it resides in .
a. $t1
b. $t2

$t1

Which improvement has a bigger impact on power?
a. 25% reduction in voltage
b. 25% reduction in frequency switching

25% reduction in voltage

A terabyte is one _____ bytes.
a. Thousand
b. Million
c. Billion
d. Trillion

trillion

The collection of software on a computer that provides services to application software.
a. System software
b. Application software
c. Compiler

system softwarfe

Computers use binary because binary is more powerful than decimal numbers.
a. True
b. False

false

Although binary's alphabet contains only two "letters", 0 and 1, the binary alphabet can represent as
much information as the English alphabet's 26 letters.
a. True
b. False

true

The corresponding binary representation of number 5C in hexadecimal is ___.
a. 10101110
b. 01011101
c. 01011100
d. 10111100

01011101

An advantage of a high-level language (HLL) is allowing a programmer to ________
a. Think more naturally
b. Think like a machine

think more naturally

Computer A requires 10 seconds to compress a file. Computer B requires 5 seconds. Which computer has
the higher performance?
a. A
b. B

B

To determine how many times faster Computer C is than Computer D, which is the correct calculation?
a. PerfC / PerfD
b. PerfD / PerfC

PerC/PerfD

As clock rates increase in early Intel Processors, power

increased

Instructions, as well as data, can be stored in memory as numbers

true or false

true

Multiple operations are allowed per MIPS instruction

true or false

false

Since registers are faster to access than memory, the compiler should keep all used variables in registers
a. True
b. False

false

Indicate whether name $t11 refers to a MIPS register
a. True
b. False

false

Indicate whether name Memory[0] refers to a MIPS register.
a. True
b. False

false

Indicate whether lw $s1, 20($s6) is a valid MIPS instruction.
a. True
b. False

true

Assume $s3 has 5000, and words addressed 5000..5002 have the data shown: 5000: 99

5001: 77

5002: 323

Assume $s0 as 5001. What value will be put in $t1 by lw $t1, 1($s0)

77

88

323

99

323

Consider the 32-bit binary number 11100000 11000000 00000000 00000001, stored in the word with address 5000. For a big-endian architecture, what value is stored in byte 5001?
a. 11100000
b. 00000000
c. 00000001
d. 11000000

11000000

Consider the 32-bit binary number 11100000 11000000 00000000 00000001, stored in the word with address 5000. For a little-endian architecture, what value is stored in byte 5003?
a. 11100000
b. 00000000
c. 00000001
d. 11000000

11100000

If $s3 has 900, $t0 has 77, and memory locations 900, 904, and 908 have 10, 15, 20 respectively, what does location 900 have after the following instruction? sw $t0, 8($s3)
a. 10
b. 15
c. 20
d. 77

10

If $s3 has 900, $t0 has 77, and memory locations 900, 904, and 908 have 10, 15, 20 respectively, what does location 904 have after the following instruction? sw $t0, 8($s3)
a. 10
b. 15
c. 20
d. 77

15

If $s3 has 900, $t0 has 77, and memory locations 900, 904, and 908 have 10, 15, 20 respectively, what does location 908 have after the following instruction? sw $t0, 8($s3)
a. 10
b. 15
c. 20
d. 77

77

Given the following 32-bit number, what is the most significant bit's value?

1000 0000 0000 0000 0000 0000 0000 0000
a. 0
b. 1

1

In two's complement, is the following number positive or negative? 1111 0000 0000 0000 0000 0000 0000 0000
a. Positive
b. Negative

negative

Knowing that 231 is 2,147,483,648, what is the base ten value of the following two's complement number? 1000 0000 0000 0000 0000 0000 0000 0000
a. 0
b. -1
c. 1
d. 2,147,483,648
e. -2,147,483,648

-2,147,483,648

For both add and addi instructions, field 3 (rt) represents a register.
a. True
b. False

true

Opcode 0 and a funct field of 32 indicates a(n) _____ instruction.
a. Add immediate
b. Add
c. Sub
d. Logic AND

add

Opcode 43 indicate a(n) ___ instruction

sub

add

sw

lw

sw

For the MIPS instruction lw $t0, 32($s3) assuming the opcode for lw is 35, the correspond machine code represented in Hexadecimal is .
a. 6E5A0020
b. 4E680020
c. 8E680020
d. None of above

8E680020

add $t0, $s1, $s2

0000 0000 0000 0000 0000 1101 1100 0000

0000 0000 0000 0000 0011 1100 0000 0000

For above add instruction, what is the corresponding output in HEX for the above two given source operands?
a. 00002B00
b. 02324020
c. 000049C0
d. None of above

000049C0

op rs rt rd shamt funct

0 8 9 10 0 34

What MIPS instruction does above represent?
a. Sub $t0, $t1, $t2
b. Add $t2, $t0, $t1
c. Sub $t2, $t1, $t0
d. Sub $t2, $t0, $t1
e. None of above

Sub $t2, $t0, $t1

For the MIPS instruction sw $t0, 1200($t1) assuming the opcode for sw is 43, the correspond machine code represented in Hexadecimal is .
a. AD5800B0
b. AD2804B0
c. 8E680020
sll $t2, $s0, 4

AD2804B0

sll $t2, $s0, 4

What is the register number of rs for the above MIPS instruction?
a. 00000
b. 10000
c. 01010
d. 00100

00000

sll $t2, $s0, 4

What is the register number of rt for the above MIPS instruction

a. 00000
b. 10000
c. 01010
d. 00100

10000

sll $t2, $s0, 4

What is the register number of rd for the above MIPS instruction

a. 00000
b. 10000
c. 01010
d. 00100

01010

$a0-$a3, $v0, $v1, and $t0-$t9 are the only registers used by the compiler to handle procedure calling.
a. True
b. False

false

What is the binary representation for a 16 bit negative 21?
a. 0000 0000 0001 0101
b. 1111 1111 1110 1010
c. 0000 0000 0000 1011
d. 1111 1111 1110 1011
e. None of above

1111 1111 1110 1010

What is the value of the register $t0 after executing the instruction slt $t0, $s0, $s1 when $s0 = 1101 and $s1 = 0010?

a. 0
b. 1
c. -1
d. None of above

1

What is the value of the register $t0 after executing the instruction sltu $t0, $s0, $s1 when $s0 = 1101 and $s1 = 0010?

a. 0
b. 1
c. -1
d. None of above

0

What is the value of the register $t1 after executing the instruction sll $t1, $s3, 2 when $s3 = 1101 0011 1101 0000 0111 1100 1000 0011 for above MIPS codes?
a. D3D07C83
b. 43D07C8C
c. 4F41F20C
d. None of above

4F41F20C

Assume $s1 has 50 and $s2 has 30. Given this code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit 8
Else: sub $s0, $s1, $s2
Exit:

If $s3 is 9 and $s4 is 9, which instruction executes after bne?
a. Add
b. Sub
c. J
d. Else

Add

Assume $s1 has 50 and $s2 has 30. Given this code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:

If $s3 is 9 and $s4 is 9, what value will $s0 have after executing the above MIPS codes
a. 30
b. 80
c. 20
d. 50

80

Assume $s1 has 50 and $s2 has 30. Given this code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit

If $s3 is 9 and $s4 is 8.9, which instruction executes after bne?
a. Add
b. Sub
c. J
d. Else

sub

Assume $s1 has 50 and $s2 has 30. Given this code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:

j Exit is executed when $s3 and $s4 value

are not equal

are equal

are equal

The first part of a main program call procedure Power to compute xy, where x is in $s0, y is in $s1. Later the program is to call Power again, but this time z is in $s3 and y is in $s7. How might the program pass the parameter values to Power

Copy $s3 to $a0, and $s7 to $a1

Not possible, x and y must be in $s0 and $s1

Copy $s3 to $a0, and $s7 to $a1

A main program calls a Power procedure using the instruction: jal Power. That instruction is at address 1000. What happens to $ra?
a. Nothing; jal is unrelated to $ra
b. $ra is set to 1000
c. $ra is set to 1004

$ra is set to 1004

A procedure Power computes $a0 to the power of $a1. How should the procedure jump back to the next instruction in the caller?
a. jr caller
b. jr $ra
c. jal $ra

jr $ra

What is $s0 after: lui $s0, 7?
a. 0000 0000 0000 0000 0000 0000 0000 0111
b. 0000 0000 0000 0000 0000 0000 0111 0000
c. 0000 0000 0000 0111 0000 0000 0111 0000
d. 0000 0000 0000 0111 0000 0000 0000 0000
e. 0000 0000 0000 1111 0000 0000 0000 0000

d. 0000 0000 0000 0111 0000 0000 0000 0000

What is $s0 after executing the following MIPS codes? lui $s0, 7 ori $s0, $s0, 8
a. 0000 0000 0000 0000 0000 0000 0000 1111
b. 0000 0000 0000 0000 0000 0000 0111 1000
c. 0000 0000 0000 0111 0000 0000 0111 0000
d. 0000 0000 0000 0111 0000 0000 0000 1000
e. 0000 0000 0000 1111 0000 0000 0000 0000

d. 0000 0000 0000 0111 0000 0000 0000 1000

Assume $s0 has 5000, and words addressed 5000..5002 have the data shown: 5000: 99

5001: 77

5002: 323

What address will computed by lw $t0, 2($s0)

5001

5002

5000

5002

Assume $s1 has 50 and $s2 has 30. Given this code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:

if $s3 is 9 and $s4 is 8.9 what value will $s0 have after executing the above MIPS codes?

50

30

20

80

20

Assume $s1 has 50 and $s2 has 30. Given this code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:

if $s3 is 9 and $s4 is 9, which instruction executes after beq

Exit

Else

Sub

Add

J

add

For the beq instruction, branch taken is referred to the situation where the branch target address becomes the new PC when the condition is true.
a. True
b. False

true

In the MIPS architecture for a branch instruction, the branch target address is given by .
a. sum of the offset field of the instruction and the address of the instruction following the branch.
b. the offset field of the instruction
c. the address of the instruction following the branch

sum of the offset field of the instruction and the address of the instruction following the branch.

Which of the following is correct for an load instruction referring to the right datapath?
a. MemtoReg should be set to cause the read data from the data memory to be sent to the register file
b. MemtoReg should be set to cause the ALUresult to be sent to the register file
c. MemtoReg should be set to cause the Readdata2 from RF to be register file

MemtoReg should be set to cause the read data from the data memory to be sent to the register file

Which of the following is correct for an R-type instruction datapath?  

a. PCSrc should be set to cause the branch target address to be written into the PC

b. PCSrc should be set to cause the sequential following instruction with address PC to be written into the PC

c. PCSrc should be set to cause the sequential following instruction with address PC+4 to be written into the PC

c. PCSrc should be set to cause the sequential following instruction with address PC+4 to be written into the PC

Which of the following is correct for a store instruction?

a. ALUSrc should be set to cause the Readdata2 from the RF to be sent to the ALU as the second input

b. ALUSrc should be set to cause the sign-extended 16-bit offset field from the instruction to be sent to the ALU as the second input

c. ALUSrc should be set to cause the Readdata1 from the RF to be sent to the ALU as the second input

d. We do not care about the setting of ALUSrc for loads

ALUSrc should be set to cause the sign-extended 16-bit offset field from the instruction to be sent to the ALU as the second input

Which of the following is correct for an R-type instruction?

a. ALUSrc should be set to cause the Readdata2 from the RF to be sent to the ALU as the second input

b. ALUSrc should be set to cause the sign-extended 16-bit offset field from the instruction to be sent to the ALU as the second input

c. We do not care about the setting of ALUSrc for loads

d. ALUSrc should be set to cause the Readdata1 from the RF to be sent to the ALU as the second input

ALUSrc should be set to cause the Readdata2 from the RF to be sent to the ALU as the second input

The single-cycle datapath conceptually must have separate instruction and data memories due to the fact that  ______. 

a. Having separate memories is less expensive

b. The formats of data and instructions are different in MIPS, and hence different memories are needed

c. The processor operates in one cycle and cannot use a single-ported memory for two different accessed within that cycle

The processor operates in one cycle and cannot use a single-ported memory for two different accessed within that cycle

The MIPS ALU defines five different arithmetic and logic operations depending on four ALU control inputs. For the branch equal operation, the four ALUctl lines should be  _____.

a. 0010

b. 0111

c. 0000

d. 0110

0110

The MIPS ALU defines five different arithmetic and logic operations depending on four ALU control inputs. For the store word instructions, the four ALUctl lines should be ______.

a. 0010

b. 0111

c. 0000

d. 0110

0010