Chapter 26: Reduced Instruction Set Computers (RISC) and Pipelining

Vocabulary flashcards covering key RISC and pipelining terms from Lecture 11.

Reduced Instruction Set Computer (RISC)

CPU design philosophy emphasizing a limited, simple instruction set, large register file, and efficient pipelining.

General-purpose registers

A large set of CPU registers used to hold operands and results, reducing memory access frequency.

Compiler register optimization

Technique where the compiler schedules and allocates variables to registers to maximize register usage efficiency.

Limited instruction set

Design choice in RISC architectures to include only essential, simple instructions for faster execution and easier decoding.

Instruction pipeline

Hardware mechanism that overlaps the execution phases of multiple instructions to improve throughput.

Machine cycle (RISC)

Time needed to fetch operands from registers, execute an ALU operation, and store the result back to a register.

Load/Store architecture

RISC feature where only LOAD and STORE instructions access memory; all other operations are register-to-register.

Register-to-register operation

Instruction that reads operands from registers, performs an ALU operation, and writes the result to a register.

Simple addressing modes

Restricted set of ways to specify operand addresses, simplifying the control unit and instruction decoding.

Fixed instruction length

Property where every instruction occupies the same number of bits and aligns on word boundaries, allowing parallel decode.

I Stage (Instruction Fetch)

Pipeline stage that retrieves the next instruction from memory.

E Stage (Execute)

Pipeline stage where the ALU performs arithmetic or logic operations using register operands.

D Stage (Memory)

Pipeline stage that carries out memory access for LOAD or STORE instructions.

Two-stage pipeline

RISC pipeline variant with Instruction Fetch (I) and Execute (E) stages for register-to-register instructions.

Three-stage pipeline

Pipeline allowing two memory accesses per stage (I, E, D), enabling overlap of up to three instructions.

Four-stage pipeline

Pipeline that splits Execute into E1 (register read) and E2 (ALU + register write), accommodating up to four concurrent instructions.

Delayed branch

Optimization where a branch instruction takes effect after the execution of the following instruction, creating a delay slot.

Delay slot

Instruction position immediately after a branch where an independent instruction can be placed to avoid pipeline stalls.

Delayed load

Technique where the target register of a LOAD is locked; execution continues until an instruction needs that register.

Loop unrolling

Optimization that replicates a loop body multiple times (unrolling factor u) to decrease branch overhead and increase ILP.

Unrolling factor (u)

Number of times the loop body is duplicated in a loop-unrolling optimization.

E1 stage

First sub-stage of Execute, responsible for reading operands from the register file.

E2 stage

Second sub-stage of Execute, performing the ALU operation and writing results back to registers.