Fetch-Execute cycle - Order of Events

Fetch - 1

PC content transferred to MAR

2

Address bus transfers MAR content to Main memory

3

Addressed memory location content loaded to MBR via Data bus

4

PC incremented, simultaneously fetches

5

Transfer MBRs content to the CIR

Decode - 6

CIR contents send to CU to decode the instruction

7

CU splits instruction into opcode and operand