Comparison Instructions

Comparison Instructions

Instructions that do not store a result but instead update condition flags in the Program Status Register.

Purpose of Comparison Instructions

To test register values and control program flow using condition codes and conditional branches.

CMP (Compare)

Subtracts an operand from a register and updates condition flags without storing the result.

Typical Use of CMP

Checking whether a register equals a specific value, such as at the start or end of a loop.

CMP Operation

Performs: Rn − operand2, updates flags only.

CMN (Compare Negative)

Adds an operand to a register and updates condition flags without storing the result.

CMN as the Inverse of CMP

CMN performs addition instead of subtraction; the assembler may replace CMP with CMN automatically.

Assembler Optimization Example (CMP to CMN)

CMP r0, #-20 is converted by the assembler to CMN r0, #0x14.

To simplify instruction encoding and improve efficiency for certain immediate values.

Why does CMN Exists?

TST (Test)

Performs a logical AND between a register and an operand and updates condition flags.

Updates N, Z, and C flags, but does not affect the V flag

Flags Affected by TST

Typical Use of TST

Checking whether specific bits in a register are set or clear.

TEQ (Test Equivalence)

Performs a logical XOR between a register and an operand and updates condition flags.

Updates N, Z, and C flags, but does not affect the V flag.

Flags Affected by TEQ

Typical Use of TEQ

Checking whether two values are equal by testing if their XOR result is zero.

TEQ Equality Test Rule

If the XOR result is zero, the Z flag is set, indicating equality.

instruction{<cond>} <Rn>, <operand2>

General Syntax of Comparison Instructions

operand2 (Comparison Instructions)

Can be a register with an optional shift or an immediate value.

Conditional Execution with Comparison Instructions

Comparison instructions are commonly followed by conditional branches like BEQ, BNE, etc.

Program Status Register (PSR)

Holds condition flags and other processor state information.

MRS (Move PSR to Register)

Copies status register contents into a general-purpose register.

MSR (Move Register to PSR)

Writes values from a general-purpose register into the status register.

ARM7TDMI Status Registers

Includes a CPSR (Current Program Status Register) and multiple SPSRs (Saved Program Status Registers).

Reading ARM7TDMI Status Registers

MRS r0, CPSR reads CPSR,
MRS r1, SPSR reads SPSR.

ARM7TDMI SPSR Restriction

Accessing an SPSR in User mode is invalid and results in UNPREDICTABLE behavior.

Register Restriction for MRS

Register r15 (PC) cannot be used as the destination for MRS.

Cortex-M4 Status Register Structure

Has a single status register accessible through APSR, IPSR, EPSR, or PSR views.

APSR (Application PSR)

The only Cortex-M4 status view that contains condition flags.

Reading Flags on Cortex-M4

MRS r3, APSR reads flag values into r3.

Writing Flags on Cortex-M4

MSR APSR, r2 updates only the flags.

Writing Full Status on Cortex-M4

MSR PSR, r7 writes all status information.

Practical Use of Flags in Programs

Flags are usually consumed immediately by conditional instructions rather than read explicitly

Why Direct Flag Reading Is Rare

Conditional branches make control flow simpler and more efficient than manually inspecting flags.

Typical Control Flow Pattern

Comparison instruction → conditional branch → loop or decision logic.