Introduction to HDL Prelim 1

Hardware Description Language

A set of notations, similar to software programming languages, used for modeling the logical function of digital circuits and systems.

Field-programmable gate array (FPGA)

An integrated circuit designed to be configured as "field-programmable" by a customer or a designer after manufacturing.

IOB

Input/Output Block (Programmable pins)

CLB

Configuration Logic Block (Programmable Gates)

In programming languages

The processor will execute lines of code one at a time, following the top-to-bottom organization that we use when reading text on a page.

In HDL code

Describing digital hardware, and separate portions of this hardware can operate simultaneously, although the corresponding lines of code are written using a top-to-bottom organization.

Abstraction

An important concept in engineering design that allows us to specify how systems will operate without getting overburdened with specific implementation details.

System Level

At this level, the behavior of a system is described by stating a set of broad specifications.

Algorithmic Level

At this level, the specifications begin to be broken down into sub-systems, each with an associated behavior that will accomplish a part of the primary task.

Register Transfer Level

At this level, the details of how data is moved between and within sub-systems are described. Also, data is manipulated based on system inputs.

Gate level

At this level, the design is described using basic gates and registers (or storage elements).

Circuit Level

This level describes the operation of the basic gates and registers using transistors, wires, and other electrical components such as resistors and capacitors.

Material Level

This level describes how different materials are combined and shaped to implement the transistors, devices, and wires from the circuit level.

Simulation

Interpretation of the HDL statements to produce human-readable output, such as timing diagrams.

Synthesis

Compilation of high-level behavioral and structural HDL statements into a flattened gate- level connection (netlist), which can then be used directly either to layout a printed circuit board, to fabricate a custom integrated circuit, or to program a programmable logic device (PLDs).

Verilog

Developed by Gateway Design Automation as a proprietary language for logic simulation in 1984. It became an IEEE standard in 1995 and was updated in 2001 [IEEE 1364-01].

VHDL (Very High-Speed Integrated Circuits Hardware Description Language or VHSIC HDL)

Was originally developed in 1981 by the Department of Defense to describe the structure and function of hardware.

SystemVerilog

Was introduced in 2005 [IEEE 1800-2009], which streamlines many of the annoyances of Verilog and adds high-level programming language features.

Inertial Delay

Swallow pulses much narrower than the delay amount.

Transport Delay

Let all pulses pass through irrespective of their width.

Concurrent system

Many process signals can happen at the same time.

Efficiency handling

Only one process at a time can be accessed.

Analysis

Syntax of hardware description is checked and interpreted

Elaboration

This is a preparatory step that sets up a hierarchically described circuit for simulation.

Simulation

Event-driven simulation is carried out.

Signal Update

Maintains a time-ordered queue of signals which are waiting to acquire their assigned values.