CMSC 311 Exam 2 Flashcards

LC-3 Address Space (LC-3 Basics)

2¹⁶ = 65,536 memory locations

LC-3 Word Size (LC-3 Basics)

16 bits

Number of General Purpose Registers (LC-3 Basics)

8 (R0–R7), each 16 bits

Number of LC-3 Instructions (LC-3 Basics)

15

Instruction Size (LC-3 Basics)

16 bits

Opcode Size (LC-3 Basics)

4 bits

Opcode Behavior (LC-3 Basics)

Each opcode interprets operand bits based on its instruction type

Immediate Addressing (Addressing Modes)

Operand value is inside the instruction

Register Addressing (Addressing Modes)

Operand is stored in a register

PC-Relative Addressing (Addressing Modes)

Address = PC + offset

Indirect Addressing (Addressing Modes)

Instruction points to a memory location that contains the address

Base+Offset Addressing (Addressing Modes)

Address = Base register + offset

PC-Relative (Data Movement)

Used in LD/ST

Indirect (Data Movement)

Used in LDI/STI

Base+Offset (Data Movement)

Used in LDR/STR

NZP Flags (NZP)

Condition codes: Negative, Zero, Positive

NZP Behavior (NZP)

Set based on result of last operation

Purpose of NZP (NZP)

Used for conditional branching

Operate Instructions (Instruction Types)

Perform calculations (ADD, AND, NOT)

Data Movement Instructions (Instruction Types)

Load/store data

Control Instructions (Instruction Types)

Change program flow (BR, JMP)

Input/Output Instructions (Instruction Types)

Handle I/O (TRAP)

LD (Load Operations)

Loads from PC-relative address

LDI (Load Operations)

Loads from address found in memory (indirect)

LDR (Load Operations)

Loads using base register + offset

ST (Store Operations)

Stores to PC-relative address

STI (Store Operations)

Stores indirectly

STR (Store Operations)

Stores using base register + offset

Conditional Branch (Branching)

Depends on NZP flags

Unconditional Branch (Branching)

Uses all flags (BRnzp) or always executes

Label (Assembly)

Symbolic name representing a memory address

Pseudo-op (Assembly)

Instruction for assembler only (not machine code)

Purpose of Pseudo-ops (Assembly)

Help define data and structure program

.ORIG (Pseudo-ops)

Starting address

.END (Pseudo-ops)

End of program

.FILL (Pseudo-ops)

Stores a value in memory

.BLKW (Pseudo-ops)

Reserves block of memory

.STRINGZ (Pseudo-ops)

Stores string ending with x0000

Pass 1 (Assembly Process)

Assign addresses to labels

Pass 2 (Assembly Process)

Convert instructions to machine code

Why Two Passes? (Assembly Process)

Labels must be known before encoding

Assembly to Machine Code (Assembly Process)

Converts symbolic instructions into binary

Subroutine (Subroutines)

Reusable block of code

Caller (Subroutines)

Code that calls subroutine

Callee (Subroutines)

Subroutine being called

JSR (JSR vs JSRR)

Uses PC-relative addressing

JSRR (JSR vs JSRR)

Uses base register

Common Feature (JSR vs JSRR)

Both store return address in R7

RET (RET Instruction)

Returns using address in R7

Why “Fake” (RET Instruction)

Actually implemented as JMP R7

Caller Save (Saving Registers)

Caller saves registers before call

Callee Save (Saving Registers)

Subroutine saves registers

Stack (Stack Basics)

LIFO (Last In First Out) structure

Stack Pointer (SP) (Stack Basics)

Points to top of stack

Where SP is Stored (Stack Basics)

Typically R6

Stack Behavior (Stack Basics)

Grows/shrinks via pointer, memory doesn’t move

Push (Stack Operations)

Decrement SP, store value

Pop (Stack Operations)

Load value, increment SP

Stack Overflow (Errors)

Stack exceeds memory bounds

Stack Underflow (Errors)

Removing from empty stack

String Format (Strings)

ASCII characters ending with x0000

Privilege (Privilege & Priority)

Level of access to system resources

Priority (Privilege & Priority)

Determines which interrupt is handled first

User Mode (Modes)

Limited access

Supervisor Mode (Modes)

Full system access

PSR (PSR)

Stores privilege bit, priority, condition codes

User Space (Memory Spaces)

Accessible by user programs

System Space (Memory Spaces)

Reserved for OS

Two Stacks (Stacks)

User stack + Supervisor stack

Each Stack (Stacks)

Has its own SP

Memory-Mapped I/O (I/O)

Devices accessed like memory

Polling (Polling)

Continuously checking device status

Why Inefficient (Polling)

Wastes CPU cycles

KBDR / DDR (Device Registers)

Hold input/output data

KBSR / DSR (Device Registers)

Status registers

Why System Calls Needed (System Calls)

User programs can’t directly access hardware

TRAP (TRAP Instruction)

Switches to supervisor mode and runs service routine

RTI (RTI Instruction)

Returns from interrupt, restores state

Interrupt-Driven I/O (Interrupts)

CPU reacts only when needed

Why Efficient (Interrupts)

No constant checking

Condition 1 (Interrupt Conditions)

Device requests interrupt

Condition 2 (Interrupt Conditions)

Interrupts enabled

Condition 3 (Interrupt Conditions)

Priority is high enough

INT Line Check (INT Line)

Checked after each instruction

If Active (INT Line)

Processor handles interrupt

Interrupted Program Awareness (Interrupts)

Program doesn’t know it was interrupted because state is restored