CMPEN 331 Exam 2 Lecture 9

control unit

The [blank] is responsible for setting all the
control signals so that each instruction is executed
properly.

• The input is the 32-bit instruction word.
• The outputs are signals to the datapath.

Most of the signals can be generated from the
instruction opcode alone, and not the entire 32-bit
word.

To illustrate the relevant control signals, we will show
the route that is taken through the datapath by R-
type, lw, sw, and beq instructions.

The speed of this unit is critical to clock cycle time (CCT)

to generate control signals

The control unit needs 13 bits of inputs.
• Six bits make up the instruction’s opcode.
• Six bits come from the instruction’s func field.
• It also needs the Zero output of the ALU.

The control unit generates 10 bits of output, corresponding to the signals mentioned on the previous slide.

You can build the actual circuit by using different strategies.

single cycle clock cycle

Uses the clock cycle inefficiently – the clock cycle must be
timed to accommodate the slowest instruction
• especially problematic for more complex instructions like floating
point (FP) multiply

May be wasteful of area since some functional units (e.g.,
adders) must be duplicated since they can not be shared
during a clock cycle
but

Single cycle datapath is simple and easy to understand

Not used much today (mainly due to very long CCT)

datapath

contains all the functional units and
connections necessary to implement an instruction set
architecture • For our single-cycle implementation, we use two separate
memories, an ALU, some extra adders, and lots of multiplexers.
• MIPS is a 32-bit machine, so most of the buses are 32-bits wide

control unit

tells the datapath what to do, based on
the instruction that’s currently being executed.
• Our processor has ten control signals that regulate the datapath.
• The control signals can be generated by a combinational circuit
with the instruction’s 32-bit binary encoding as input.

single cycle

type of cycle where:

• CPI: always 1
• All the instructions have same speed
• Clock cycle: long (governed by the slowest instruction)

• each instruction takes one clock cycle

multi cycle

type of cycle where:

• CPI > 1 (depends on instruction type)
• Faster instructions finish earlier
• Clock cycle: short (governed by the slowest stage)

• each stage takes one clock cycle

pipelining

• Start fetching and executing the next instruction before
the current one has completed

• Under ideal conditions and with a large number of
instructions, the speedup from pipelining is
approximately equal to the number of pipe stages

• Fetch (and execute) more than one instruction at a time

pipelining

• Divide the instruction processing cycle into distinct “stages” of
processing
• Ensure there are enough hardware resources to process one
instruction in each stage
• Process a different instruction in each stage
• Instructions consecutive in program order are processed in consecutive
stages

• Benefit: Increases instruction processing throughput
(IPC=1/CPI)
• Outside the memory system, the effective operation of the
pipeline is usually the most important factor in determining the
CPI of the processor
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a pipelined MIPS processor

Start the next instruction before the current one has
completed
• improves throughput - total amount of work done in a given time
• instruction latency (execution time, delay time, response time –
time from the start of an instruction to its completion) is not
reduced and may increase slightly

• clock cycle (pipeline stage time) is limited by the slowest stage
• for some stages don’t need the whole clock cycle (e.g., WB)
• for some instructions, some stages are wasted cycles (i.e., nothing is done during that cycle for that instruction)

structural hazards

attempt to use the same resource by two
different instructions at the same time

data hazards

attempt to use data before it is ready
• An instruction’s source operand(s) are produced by a prior
instruction still in the pipeline

control hazards

attempt to make a decision about program
control flow before the condition has been evaluated and the
new PC target address calculated
• branch and jump instructions, exceptions