CMPEN 331 Exam 2 Lecture 8

fetch

get the bits representing the current instruction from MEM[PC]

decode

figure out which instruction has been fetched:
• What type? (R, I, J) What resources are needed (Mem, Imm, Reg)?
• Get local register operands; sign extend immediates; concat J-type IMM, PC

execute

perform arithmetic/ logical operation specified by the instruction
• express necessary control to employ arithmetic logic unit (e.g. +, -, &) if necessary
• may need different functionality, additional HW, for each instruction class

memory

perform read/write
• only relevant for load/store variants

writeback

update any state with modified values
• update registers, if any

instruction and data memories

• two types of memory
• the separation is only conceptual (von neumann, they are the same), physical (harvard, they are two different memories), or in between (same memory but separate cache, harvard)
• most modern computers are harvard architecture

components: instruction memory

• input: address
• output: instruction in that address

components: register files

when reading:
• input: two register numbers
• output: values in the register

when writing (controlled by RegWrite signal):
• input: register number, value
• writes the value to the register

components: ALU

• input: two values
• output: computation output using the two values
• type of computation controlled by ALU operation signal

components: data memory

when reading (controlled by MemRead signal):
• input: address
• output: value in the address

when writing (controlled by the MemWrite signal):
• input: address, value
• writes the value to the address

components: others

• mux: chooses one of the inputs and connect it to the output
• sign-extend: do sign-extension

PC (program counter)

a specialized register that holds the address of the instruction to execute

instruction fetch

instructions involve:
• reading the instruction from the instruction memory that PC points to
• updating PC to point to the next instruction
• if not branch/jump, next PC = current PC + 4
• automatically updated on every clock cycle

decoding instructions: getting register operands

instructions involve:
• understanding what instruction must be executed and getting signals to control relevant components (e.g. registers, ALU, memory) --- op/func code
• reading two registers --- rs/rt
• who reads the two register? R-type, some I-types (beq/bne, lw)
• Who reads one register? Other I-types (sw, addi)
• Who reads zero register? J-type
• What if the instruction does not use rs/rt? Still read something and don't use. It won't hurt

executing R-Format instructions
• (add, sub, alt, and, or)

how to execute a certain type of instruction:
• perform operation (op and funct) on values rs and rt
• store the result back into the register file (into location rd)
• note that the register file is not written every cycle (e.g. instruction that are not this type), so we need an explicit write control signal for the register file

executing load and store operations

how to execute two specific operations:
• for both: compute the effective memory address by adding the contents of the base register (read from the Register File during decode) to the 16-bit-sign-extended immediate field (byte offset) in the instruction

for one of them only:
• value, (read from the Register File during decode) written to the Data Memory

for the other only:
• value, read from the Data Memory, written to the Register File

branch instructions

specific type of instructions:
• read register operands
• compare operands; use ALU (can subtract and check "zero" output)
• calculate target address
• sign-extend displacement
• shift left 2 places (word displacement -> byte displacement)
• add to PC + 4
• already calculated by fetch
• MIPS was always designed with pipelining in mind

implementing J-Type Jumps
• blank = jump

implementing a specific instruction:
• uses word address
• update PC with concatenation of
• top 4 bits of old PC
• 26-bit [blank] address
• lower bits word-aligned: 2'b00
• need an extra control signal decoded from opcode

ALU control

used for:
• load/store: F = add
• branch: F = subtract
• R-Type: F depends on funct field