A Level Computer Science- 1.1 Characteristics of Processors

Control Unit

Coordinates activities in the CPU

Program Counter

Holds address of memory location of next address to be executed, while simultaneously incrementing

MAR

Holds address of the memory location from which data is fetched or written

MDR

Temporarily stores data which is read/written to memory

CIR

Holds current instruction being executed

ALU

Performs logical and arithmetic operations

FDE Cycle

PC→MAR→RAM→MDR→CIR→ALU→ACC

Data bus

Transfers data/instructions between the MDR and RAM. Bi-directional

Address Bus

Transfers address of memory location of data bus to be fetched between the MAR and RAM, one direction.

Control Bus

Sends control signals between the CU and RAM

Von Neumann Architecture

Shared memory space for data and instructions,
Single CU follows linear FDE cycle
One instruction at a time
Registers used as fast access to data

Advantages/Disadvantages of Von Neumann

Advantages: Simpler design, Programs can be stored as data meaning that they are represented the same way as regular data, Easier to implement in general-purpose devices.

Disadvantages: Only one transfer can happen at a time, so CPU has to wait, Slower performance

Harvard Architecture

Instructions and data stored in separate memory units

Each memory unit has its own bus
Read/write data can be done while fetching an instruction
Used by RISC processors

Advantages/Disadvantages of Harvard architecture

Advantages: Faster, No chance of overwriting instructions as data, Useful for performance critical systems, e.g. medical equipment.

Disadvantages: Expensive, Harder to program, not flexible for general purpose

CISC Processor

Complex Instruction set Computer
complex hardware
multiple clock cycles per instruction
more expensive
good for intensive tasks
fewer ways to address memory
used in general purpose devices

RISC Processor

Reduced Instruction Set Computer
cheaper to make
single cycle per instruction
can perform simpler tasks quickly
simpler hardware
many ways to address memory

Multicore System

A single chip that contains two or more independent processing units, each with its own registers and components, and cache. There is also a shared cache available. Each core can do an FDE cycle

Parallel Processing

Processing of instructions by dividing them between multiple processor cores. Means multiple tasks can be done at once, running a program in less time

Detailed FDE cycle.

Program Counter holds address of next instruction → the address is copied to MAR → address sent along address bus to main memory → MDR receives data from memory via data bus → Instruction copied into CIR → PC Increments by 1. → CU interprets instruction in CIR with opcode and operand, using the decode unit → uses ALU to perform calculations which are stored in the ACC, or loads/stores data.

Cache affecting performance

 The more frequently used instructions  that are stored, the quicker they can be fetched, increasing the performance.

No. of cores

Multicore processors allow for parallel processing, so the more cores, the more tasks can be performed at once, increasing performance.

Clock speed 

Clock speed refers to the number of FDE cycles that can be done per second. Higher clock speeds means more FDE cycles per second, increasing performance

Size of Registers

Registers store data and instructions. The larger the registers, the more they can process

Size of RAM

Allows computers to store more files, allowing the computer to run multiple programs at once.

Optical Storage

Storage data that is read back using light from a laser

Magnetic Storage

Data that is stored on a magnetized medium

Solid State

Uses circuit assemblies to persistently store data