cpu structure instruction

CPU

What is cpu organisation in computer architecture?

The srtucture and function of CPU

What is the key component for CPU organization

Control Unit, Arithmathic Logic Unit, and Memory unit

state the 3 type of processor.

Explain instruction cycle.

For a single instruction that needs to be executed by the cpu, It must go throught instruction cycle

List the instruction cycle.

Fetch, Decode, Execute, memory access, and Registry write back

What is the challanges Modern CPU instruction Execution

Pipeline hazard, Branch prediction errors, instruction cache misses, Instruction, Recourse contention

What is a technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed

Instruction Pipelining

What does the Memory Unit (MU) do in a CPU?

it stores and retrieves data and instructions during execution.

How does a quad-core processor improve performance?

It allows four independent cores to execute instructions in parallel.

How does pipelining improve CPU performance?

It increases instruction throughput and resource utilization.

What is the advantages of using instruction pipelines

it is more efficient

What is a pipeline hazard?

A situation that prevents the next instruction from executing in the next cycle.

What is a data hazard?

When an instruction depends on the result of a previous instruction.

“the location of an instruction depends on previous instruction” refers to?

control hazard

What is a structural hazard?

When two instructions compete for the same hardware resource.

what is RISC stands for?

Reduced Instruction Set Computer.

What is a key characteristic of RISC architecture?

Only load and store instructions access memory; operations use registers.

What is the Decode stage in the instruction cycle?

The CPU interprets the instruction and identifies required actions.

What happens during the Execute stage?

The CPU performs the operation (calculation, comparison, or logic).

Why does RISC use fixed-length instructions?

To simplify decoding and improve pipeline efficiency.