Systems Architecture: Systems Architecture: Computer Science: GCSE (9:1)

Von Neumann

Computing pioneer from Hungary who gave his name to a computer architecture that uses stored programs. Instructions are fetched, decoded and executed one at a time.

Fetch

The phase of the instruction cycle that retrieves an instruction from main memory

Decode

This phase of the instruction cycle determines what task the CPU must perform

Execute

The phase of the instruction cycle where the task is carried out, which could be an arithmetic, shift, logic or memory operation

Fetch-Execute Cycle

Also known as the instruction cycle, the complete process of retrieving an instruction from store, decoding it and carrying it out

Instruction

A single operation, one of these is executed each time the CPU performs the fetch-execute cycle

Main memory

Also known as RAM or Primary Storage, this is where data and instructions are stored in the Von Neumann architecture

Process

Computers take input, and produce output. This is what happens in between, which needs a CPU

Stored program

Von Neumann invented this concept, it means keeping the instructions in memory instead of inputting them each time through switches or paper tape

Central Processing Unit

This component repeatedly fetches, decodes and executes instructions. Often abbreviated to CPU

Architecture

The design of a computer, including the way its components are organised and the rules that male them work together. Von Neumann invented a type of this

Memory Address Register

The register that contains an address in RAM of the next instruction or the next data item to be used, it sets up the address bus ready for a memory read or write operation.

Memory Data Register

A register that stores the data being sent to or retrieved from memory. This could be data to be processed, or an instruction being fetched.

Accumulator

A register in the ALU that holds data temporarily. It stores the results of calculations and logical operations.

Program Counter

A register that holds the address of the next instruction to be fetched during the fetch-execute cycle