1.1.1 Fetch-Execute Cycle and Registers

What is FE Cycle

Fetch-Execute Cycle

Describe it simply

Instructions are fetched from RAM, decoded to be executed by the CPU

Program Counter

holds the address of the next instruction to be executed in memory

Memory Address Register (MAR)

holds the memory address of data to be fetched or stored in RAM.

Memory Data Register (MDR)

stores the instruction that was fetched or to be written to memory

Accumulator (ACC)

stores the result of mathmatical or logical calculations

Step 1

PC sends address to MAR

Step 2

PC is increased by 1 for the next instruction, prepares the system for the next instruction to be fetched

Step 3

CPU checks RAM for the address in MAR

Step 4

The instruction is transferred to MDR

Step 5

The instruction is decoded by the control unit

Step 6

The instruction is executed by the CPU, result goes to the ACC

Step 7

Cycle repeats itself by going back to step 1