Problem Set 8/9

Just before the beginning of the execute stage

Before what pipeline stage is “branch prediction” performed?

Control Code Register

CCR

1

What will be the value of the Carry-flag if the microprocessor operation results to a carry bit.

receive the μOps provided by the front-end

In the process of out-of-order execution in a microprocessor, which of the following step needs to be performed first, before the rest?

flip-flop

This logic circuit is a fundamental building block of a microprocessor register.

FPU

Which of the following execution units is primarily tasked to perform basic addition, subtraction, multiplication, and division on floating point numbers?

Robert Noyce

Who patented the first integrated circuit on a monolithic die?

register can transfer data faster than main memory

What is the reason why assembly language programmers makes use of the general purpose registers rather than main memory?

micro-operations

Based on the Tutorial Video, what links the ISA to the microarchitecture of a CPU?

Electronic Numerical Integrator and Computer

The ENIAC was the first programmable, electronic, general-purpose digital computer, which was completed in 1945. What does the acronym ENIAC stand for?

Address Generation Unit

AGU

0

What will be the value of the Negative-flag if the microprocessor operation results to a positive number.

Grace hopper

One of the pioneers in the computer industry and in 1946 she was the first to coin the term "bug" in a computer system. Who is she?

Moore's law

What do we call the observation states that the number of transistors in a given die area for a microprocessor doubles within 18 to 24 months?

C-Flag=1, Z-flag=1

If the value of accumulator A=$EE and accumulator B=$12, what will be the value of the flags after executing the instruction ABA, which means add accumulators A and B?

PUSH operation

What do you call the process or operation that writes data into the stack?

flip-flop

This logic circuit is a fundamental building block of a microprocessor register.

Advanced Vector Extensions

AVX

fetch and decode

Which two stages in the machine cycle are referred to as the FRONT END of a microprocessor architecture?

Gaussian Neural Accelerator

GNA

Memory Address Registers

Temporarily stores the address of the next instruction that needs to be executed by the processor.

Memory Data Register

MDR

Current Instruction Register

Stores the Copy of the Instruction currently in the MDR.

floating point unit

FPU

Control Logic

is the circuit responsible in the operation of the different parts of the CPU.

Timing Circuit

used to synchronize the operation of the different parts of the CPU. It is always in phase with the clock system of the CPU.

pipeline

is a set of data processing (machine cycle) elements connected in series, where the output of one element is the input of the next one.

User-accessible registers

registers that can be read or written by machine instructions given by the users.

Internal registers

registers not accessible by instructions, used internally for processor operations.

Special purpose registers

SPR

Model/machine-specific registers (MSRs)

stores data and settings related to the processor itself.

Memory Type Range Registers (MTRRs)

provides system with control of how accesses to memory are cached by the CPU.

Hardware registers

registers not part of the CPU but are related to its function.

Memory buffer register

MBR

Memory data register

MDR

Memory address register

MAR

Stack pointer

A register that points to the top of the stack

Lookup Table

is a fundamental building block of an FPGA that is connected to a Flip-Flop. This is called

Macrocells

These are the basic output mechanisms used by programmable logic devices and provides interconnection between logic cells.

execute

Which stage in the machine cycle is responsible for carrying out computations in the ALU, transferring of data, and performing branches?

serial/sequential

The machine elements of a scalar pipeline is executed in ______manner

Fragmentation

This is a phenomenon in which storage space is used inefficiently, because of noncontinuous files, reducing capacity or performance and often both.

Pages

In the paging memory-management scheme, the operating system retrieves data from secondary storage in same-sized blocks called

ASIC

This is an integrated circuit (IC) that is fabricated for customized and of particular use, rather than intended for general-purpose use.

Logic synthesis

This is the process by which an abstract form of desired circuit behaviour is turned into a design implementation in terms of logic gates.

Field-Programmable Gate Array

FPGA

tRP

This memory timing parameter is the total time taken between Precharge command and the next Active command can be issued.

Hardware Description Language

Other than VHDL, what is the other programming language standardized to be used to program FPGAs or CPLDs?

Translation Lookaside Buffer

TLB

Programmable Logic Arrays

PLA

fetch and execute

Which stage in the machine cycle is responsible for carrying out operations involving CPU cache?

Complex Programmable Logic Device

CPLD

Write-through

Which cache Algorithm is the memory write done synchronously both to the cache and to the backing stone

$01

Based on the motorola 6800 microprocessor instruction set, what is the op-code (in HEX) of the assembly instruction with the mnemonic: NOP

8

For the Motorola 6800, how many processor clock cycles are needed to execute the BSR(Branch to sub-routine) instruction?

Arithmetic and Logic Unit

ALU

Memory Management Unit

MMU

Active to Precharge Delay (tRAS)

After an Active command is issued, another Prechargecommand cannot be issued until tRAS has elapsed.