Memory and Storage | Microprocessor | Computer | The 8051 Microcontroller

How many address bits are needed to select all memory locations in the 2118 16K × 1 RAM?
8
10
14
16

14

The check sum method of testing a ROM:
indicates if the data in more than one memory location is incorrect.
provides a means for locating and correcting data errors in specific memory locations.
allows data errors to be pinpointed to a specific memory location.
simply indicates that the contents of the ROM are incorrect.

simply indicates that the contents of the ROM are incorrect.

What is the meaning of RAM, and what is its primary role?
Readily Available Memory; it is the first level of memory used by the computer in all of its operations.
Random Access Memory; it is memory that can be reached by any sub- system within a computer, and at any time.
Random Access Memory; it is the memory used for short-term temporary data storage within the computer.
Resettable Automatic Memory; it is memory that can be used and then automatically reset, or cleared, after being read from or written to.

Random Access Memory; it is the memory used for short-term temporary data storage within the computer.

The storage element for a static RAM is the ________.
diode
resistor
capacitor
flip-flop

flip-flop

In a DRAM, what is the state of R/W during a read operation?
Low
High
Hi-Z
None of the above

High

The condition occurring when two or more devices try to write data to a bus simultaneously is called ________.
address decoding
bus contention
bus collisions
address multiplexing

bus contention

Which is/are the basic refresh mode(s) for dynamic RAM?
Burst refresh
Distributed refresh
Open refresh
Burst refresh and distributed refresh

Burst refresh and distributed refresh

One of the most important specifications on magnetic media is the ________.
rotation speed
tracks per inch
data transfer rate
polarity reversal rate

data transfer rate

A 64-bit word consists of ________.
4 bytes
8 bytes
10 bytes
12 bytes

8 bytes

Which of the following RAM timing parameters determine its operating speed?

tACC

tAA and tACS

tCO and tOD

tRC and tWC

tRC and tWC

The reason the data outputs of most ROM ICs are tristate outputs is to:
allow for three separate data input lines.
allow the bidirectional flow of data between the bus lines and the ROM registers.
permit the connection of many ROM chips to a common data bus.
isolate the registers from the data bus during read operations.

permit the connection of many ROM chips to a common data bus.

Select the statement that best describes Read-Only Memory (ROM).
nonvolatile, used to store information that changes during system operation
nonvolatile, used to store information that does not change during system operation
volatile, used to store information that changes during system operation
volatile, used to store information that does not change during system operation

nonvolatile, used to store information that does not change during system operation

How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system?
2
4
8
16

8

What is the maximum time required before a dynamic RAM must be refreshed?
2 ms
4 ms
8 ms
10 ms

2 ms

Which of the following best describes random-access memory (RAM)?
a type of memory in which access time depends on memory location
a type of memory that can be written to only once but can be read from an infinite number of times
a type of memory in which access time is the same for each memory location
mass memory

a type of memory in which access time is the same for each memory location

Why are ROMs called nonvolatile memory?
They lose memory when power is removed.
They do not lose memory when power is removed

They do not lose memory when power is removed

Which of the following best describes static memory devices?
memory devices that are magnetic in nature and do not require constant refreshing
memory devices that are magnetic in nature and require constant refreshing
semiconductor memory devices in which stored data will not be retained with the power applied unless constantly refreshed
semiconductor memory devices in which stored data is retained as long as power is applied

semiconductor memory devices in which stored data is retained as long as power is applied

Which is not a removable drive?
Zip
Jaz
Hard
SuperDisk

Hard

Which of the following best describes EPROMs?
EPROMs can be programmed only once.
EPROMs can be erased by UV.
EPROMs can be erased by shorting all inputs to the ground.
All of the above.

EPROMs can be erased by UV.

How many storage locations are available when a memory device has 12 address lines?
144
512
2048
4096

4096

FIFO(First In, First Out) is formed by an arrangement of ________.
diodes
transistors
MOS cells
shift registers

shift registers

Why do most dynamic RAMs use a multiplexed address bus?
It is the only way to do it.
to make it faster
to keep the number of pins on the chip to a minimum

to keep the number of pins on the chip to a minimum

CCD stands for ________.
capacitor charging device
capacitor-capacitor drain
charged-capacitor device
charge-coupled device

charge-coupled device

What is the major difference between SRAM and DRAM?
DRAMs must be periodically refreshed.
SRAMs can hold data via a static charge, even with power off.
The only difference is the terminal from which the data is removed—from the FET Drain or Source.
Dynamic RAMs are always active; static RAMs must reset between data read/write cycles.

DRAMs must be periodically refreshed.

Which of the following best describes volatile memory?
memory that retains stored information when electrical power is removed
memory that loses stored information when electrical power is removed
magnetic memory
nonmagnetic

memory that loses stored information when electrical power is removed

What is a major disadvantage of RAM?
Its access speed is too slow.
Its matrix size is too big.
It is volatile.
High power consumption

It is volatile.

What two functions does a DRAM controller perform?
address multiplexing and data selection
address multiplexing and the refresh operation
data selection and the refresh operation
data selection and CPU accessing

address multiplexing and the refresh operation

Dynamic memory cells store a data bit in a ________.
diode
resistor
capacitor
flip-flop

capacitor

Which is not part of a hard disk drive?
Spindle
Platter
Read/write head
Valve

Valve

ROMs retain data when the ________.
power is off
power is on
system is down
all of the above

all of the above

Typically, how often is DRAM refreshed?
2 to 8 ms
4 to 16 ms
8 to 16 us
1 to 2 us

4 to 16 ms

Which type of ROM can be erased by an electrical signal?
ROM
mask ROM
EPROM
EEPROM

EEPROM

Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in this device?
8,000
64,000
65,536
8,192

8,192

Data is written to and read from the disk via a magnetic ________ head mechanism in the floppy drive.
cylinder
read/write
recordable
cluster

read/write

What does the term "random access" mean in terms of memory?
Addresses must be accessed in a specific order.
Any address can be accessed in any order.

Any address can be accessed in any order.

How many address lines would be required for a 2K × 4 memory chip?
8
10
11
12

11

When a RAM module passes the checkerboard test it is:
able to read and write only 1s.
faulty.
probably good.
able to read and write only 0s.

probably good.

Which type of ROM has to be custom built by the factory?
ROM
mask ROM
EPROM
EEPROM

mask ROM

What is the computer main memory?
Hard drive and RAM
CD-ROM and hard drive
RAM and ROM
CMOS and hard drive

RAM and ROM

A major disadvantage of the mask ROM is that it:
is time consuming to change the stored data when system requirements change
is very expensive to change the stored data when system requirements change
cannot be reprogrammed if stored data needs to be changed
has an extremely short life expectancy and requires frequent replacement

cannot be reprogrammed if stored data needs to be changed

The periodic recharging of DRAM memory cells is called ________.
multiplexing
bootstrapping
refreshing
flashing

refreshing

Which of the following is normally used to initialize a computer system's hardware?
Bootstrap memory
Volatile memory
External mass memory
Static memory

Bootstrap memory

What is the difference between static RAM and dynamic RAM?
Static RAM must be refreshed, dynamic RAM does not.
There is no difference.
Dynamic RAM must be refreshed, static RAM does not.

Dynamic RAM must be refreshed, static RAM does not.

Microprocessors and memory ICs are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be ________.
buffered
decoded
addressed
stored

buffered

What are the typical values of tOE?

10 to 20 ns for bipolar

25 to 100 ns for NMOS

12 to 50 ns for CMOS

All of the above

All of the above

Which type of ROM can be erased by UV light?
ROM
mask ROM
EPROM
EEPROM

EPROM

Which of the following is NOT a type of memory?
RAM
ROM
FPROM
EEPROM

FPROM

How many address bits are required for a 4096-bit memory organized as a 512 × 8 memory?
2
4
8
9

9

In general, the ________ have the smallest bit size and the ________ have the largest.
EEPROMs, Flash
SRAM, mask ROM
mask ROM, SRAM
DRAM, PROM

EEPROMs, Flash

Advantage(s) of an EEPROM over an EPROM is/are:
the EPROM can be erased with ultraviolet light in much less time than an EEPROM
the EEPROM can be erased and reprogrammed without removal from the circuit
the EEPROM has the ability to erase and reprogram individual words
the EEPROM can be erased and reprogrammed without removal from the circuit, and can erase and reprogram individual words

the EEPROM can be erased and reprogrammed without removal from the circuit, and can erase and reprogram individual words

The mask ROM is ________.
permanently programmed during the manufacturing process
volatile
easy to reprogram
extremely expensive

permanently programmed during the manufacturing process

How many 1K × 4 RAM chips would be required to build a 1K × 8 memory system?
2
4
8
16

2

Which of the following memories uses a MOS capacitor as its memory cell?
SRAM
DRAM
ROM
FIFO

DRAM

Which of the following faults will the checkerboard pattern test for in RAM?
Short between adjacent cells
Ability to store both 0s and 1s
Dynamically introduced errors between cells
All of the above

All of the above

On a CD-ROM, ________ are raised areas representing a 1.
mounds
lands
holes
pits

lands

The location of a unit of data in a memory array is called its ________.
storage
RAM
address
data

address

On a CD-ROM, ________ are recessed areas representing a 0.
mounds
lands
holes
pits

pits

Why is a refresh cycle necessary for a dynamic RAM?
to clear the flip-flops
to set the flip-flops
The refresh cycle discharges the capacitor cells.
The refresh cycle keeps the charge on the capacitor cells.

The refresh cycle keeps the charge on the capacitor cells.

Which is not a magnetic storage device?
Magnetic disk
Magnetic tape
Magneto-optical disk
Optical disk

Optical disk

The time from the beginning of a read cycle to the end of tACS or tAA is referred to as:

access time

data hold

read cycle time

write enable time

access time

Which of the following memories is volatile?
ROM
EROM
RAM
Flash

RAM

The refresh period for capacitors used in DRAMs is ________.
2 ms
2 us
64 ms
64 us

2 ms

What is the principal advantage of using address multiplexing with DRAM memory?
reduced memory access time
reduced requirement for constant refreshing of the memory contents
reduced pin count and decrease in package size
It eliminates the requirement for a chip-select input line, thereby reducing the pin count.

reduced pin count and decrease in package size

What is a multitap digital delay line?

a series of inverter gates with RC circuits between each one

a series of inverter gates with RL circuits between each one

a series of NAND gates with RC circuits between each one

a series of NAND gates with RL circuits between each one

a series of inverter gates with RC circuits between each one

The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ________.
4096
8129
16358
32768

16358

How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
Eight
Four
Two
One

Eight

The mask ROM is ________.
MOS technology
diode technology
resistor-diode technology
DROM technology

MOS technology

Which of the following is not a flash memory mode or operation?
Burst
Read
Erase
Programming

Burst

The smallest unit of binary data is the ________.
bit
nibble
byte
word

bit

Select the statement that best describes the fusible-link PROM.
user-programmable, one-time programmable
manufacturer-programmable, one-time programmable
user-programmable, reprogrammable
manufacturer-programmable, reprogrammable

user-programmable, one-time programmable

How can UV erasable PROMs be recognized?
There is a small window on the chip.
They will have a small violet dot next to the #1 pin.
Their part number always starts with a "U", such as in U12.
They are not readily identifiable, since they must always be kept under a small cover.

There is a small window on the chip.

What part of a Flash memory architecture manages all chip functions?
I/O pins
floating-gate MOSFET
command code
program verify code

floating-gate MOSFET

An 8-bit address code can select ________.
8 locations in memory
256 locations in memory
65,536 locations in memory
131,072 locations in memory

256 locations in memory

Eight bits of digital data are normally referred to as a:
group.
byte.
word.
cell.

byte.byte.

Which is not a hard disk performance parameter?
Seek time
Break time
Latency period
Access time

Break time

The ideal memory ________.
has high storage capacity
is nonvolatile
has in-system read and write capacity
has all of the above characteristics

has all of the above characteristics

To which pin on the RAM chip does the address decoder connect in order to signal which memory chip is being accessed?
The address input
The output enable
The chip enable
The data input

The chip enable

EEPROM stands for ________.
encapsulated electrical programmable read-only memory
elementary electrical programmable read-only memory
electrically erasable programmable read-only memory
elementary erasable programmable read-only memory

electrically erasable programmable read-only memory

L1 is known as ________.
primary cache
secondary cache
DRAM
SRAM

primary cache

Describe the timing diagram of a write operation.
First the data is set on the data bus and the address is set, then the write pulse stores the data.
First the address is set, then the data is set on the data bus, and finally the read pulse stores the data.
First the write pulse stores the data, then the address is set, and finally the data is set on the data bus.
First the data is set on the data bus, then the write pulse stores the data, and finally the address is set.

First the data is set on the data bus and the address is set, then the write pulse stores the data.

What is the bit storage capacity of a ROM with a 1024 × 8 organization?
1024
2048
4096
8192

8192

Which of the following is one of the basic characteristics of DRAMs?
DRAMs must have a constantly changing input.
DRAMs must be periodically refreshed in order to be able to retain data.
DRAMs have a broader "dynamic" storage range than other types of memories.
DRAMs are simpler devices than other types of memories.

DRAMs must be periodically refreshed in order to be able to retain data.

The main advantage of semiconductor RAM is its ability to:
retain stored data when power is interrupted or turned off
be written to and read from rapidly
be randomly accessed
be sequentially accessed

be written to and read from rapidly

Which of the following describes the action of storing a bit of data in a mask ROM?
A 1 is stored in a bipolar cell by opening the base connection to the address line.
A 0 is stored in a bipolar cell by shorting the base connection to the address line.
A 1 is stored by connecting the gate of a MOS cell to the address line.
A 0 is stored by connecting the gate of a MOS cell to the address line.

A 1 is stored by connecting the gate of a MOS cell to the address line.

Address decoding for dynamic memory chip control may also be used for:
controlling refresh circuits
read and write control
chip selection and address location
memory mapping

memory mapping

Assume a ROM to be tested is compared with a known good ROM. If the checksums differ, the ROM is ________.
very likely to be good
definitely good
very likely to be bad
definitely bad

definitely bad

The checkerboard pattern test is used to test ________.
ROM
EEPROM
FPLA
RAM

RAM

Information that is stored in an EEPROM ________.
can be modified by performing a memory write operation
is stored by the manufacturer and cannot be changed
is lost if power is interrupted
can be erased by applying high voltage to each storage location

can be erased by applying high voltage to each storage location

The difference between RAM and ROM is that ________.
RAM has a read/write signal and ROM doesn't
RAM will lose data when the power is removed and ROM won't
RAM has random address access and ROM uses sequential address access
RAM has a read/write signal and ROM doesn't; RAM will lose data when the power is removed and ROM won't.

RAM has a read/write signal and ROM doesn't; RAM will lose data when the power is removed and ROM won't.

The TMS44100 has ________ address inputs.
10
11
12
13

11

A type of memory that is accessed serially (one location after the other) is a ________.
ROM
read/write memory
shift register
PLD

shift register

The basic purpose of tristate or open-collector outputs on a memory is to ________.
isolate devices connected to a common bus
simplify the circuitry
provide faster transitions of the output
increase the output current

isolate devices connected to a common bus

The checksum method is used to test ________.
ROM
EEPROM
FPLA
RAM

ROM

Because 4096 = 2^12, a 4K × 1 RAM requires ________ address bits to access all locations.
4096
10
12
1024

12

To reduce the number of pins on high-capacity DRAM chips, address ________ is used so that a single pin can accommodate two different address bits.
conversion
programming
multiplexing
firmware

multiplexing

The number of 16k × 4 memories needed to construct a 128k × 8 memory is ________.
4
8
12
16

16

The minimum number of address lines needed for a 64K memory is ________.
10
12
14
16

16

The 2147 4K × 1 static RAM contains 4096 storage locations storing one bit each. ________ 2147 RAM memory chip(s) is/are needed to configure an 8K × 8 memory.
One
Four
Eight
Sixteen

Sixteen

A CD-ROM is a form of read-only memory in which data are stored as ________.
magnetic "bubbles"
magnetized spots
"pits" on an optical disk
tiny "pinholes" in an opaque substance

"pits" on an optical disk

A type of read/write memory available with MOS technology is ________.
SRAM
DRAM
both of the above
none of the above

both of the above