EE1Y Digital

microcontroller

extremely compact self contained microcomputers that can only run one task at a time

microcontroller types

8-bit, 16-bit, 32-bit

microcontroller componenets

* clock
* CPU
* instruction decoder
* input/output ports
* memory

clock

keeps everything synchronised

CPU

heart of the microcontroller

instruction decoder

controls the chip and caries out each instruction

data bus

bidirectional between ROM, RAM, I/O, instruction decoder and CPU that carries the read/write memory

address bus

unidirectional from CPU to ROM, RAM or I/O that carries the address

ALU

data manipulation

registers

temporary storage of data to be manipulated

complex instruction set computer

* complete all encompassing instruction set
* many microprocessors
* simple instructions are single clock cycle
* more complex ones are several cycles

reduced instruction set computer

* reduced instruction set of simple commands
* many microcontrollers
* most commands operate in fewer clock cycles

machine language

fundamental basic instructions

assembly language

machine specific instructions

n-bits wide

eg in a 32-bit ARM each number is 32-bit ie 4 bytes wide

bus wires

eg in a 32-bit MCU there are 32 parallel wires

von Neumann architechture

all memory is held together

Harvard architechture

ROM and RAM are held separately

how many memory addresses can a 32-bit system access?

2^32 = 4GB

how many bits can each memory address hold on a 32-bit system?

32-bits

logic 1

2\.3V - 3.3V (or 5.0V)

logic 0

0\.0V - 1.0V

undefined logic level

1\.0V - 2.3V

why does a blue LED require more voltage than a red LED?

blue light is higher energy than red

LED terminals

anode and cathode

LED forward current

current flowing from anode to cathode

connecting an LED to light when logic 1

connect between Vdd and Vss

limit red LED connected to 3.3V MCU to 5mA

* V from MCU is 3.3V
* V drop across diode is 2.2V
* V remaining is 3.3 - 2.2 = 1.1V
* V=IR
* 1.1 = 0.005 x R
* 1.1/0.005 = 22 ohms

DAC output values

* Vo = (D/2^n)Vr
* Vo = analogue output voltage
* D = value of binary input word
* n = number of bits in input word
* Vr = value of the voltage reference

DAC output step size

Vr/2^n

DAC maximum output value

D = (2^n) - 1

kelvin divider

* string of resistors creates a ladder of voltages
* one of these is switched to output

weighted resistor DAC

network of different resistances each switched by the digital bits

weighted resistor DAC disadvantages

* very wide range of resistor values is needed for a large number of bits
* resistors must be high precision
* needs low resistance switches if the lowest R is small
* leads to errors for large number of bits

offset

lowest value (0V assumed)

Vref

* when least significant bit is highest value
* eg when 8-bit digital code is 1111 1111

range

largest value minus the smallest one

resolution

* smallest analogue change
* analogue different between consecutive numbers
* Vref/2^n or range/(2^n)-1 for an n-bit DAC

ADC - DAC system

* changing signal is samples at a regular time interval
* put the digital values through DAC to get the analogue output for the speakers
* sampling has caused a blockiness that needs smoothing
* low pass filter eliminates all sharp edges

pull down resistor

resistor goes between ground and the connection between the switch and MCU

pull up resistor

resistor goes between Vdd and the connection between switch and MCU

ADC output

* D = (Vi/Vr)2^n
* D = digital output value
* Vi = analogue input voltage
* Vr = reference voltage
* n = number of bits in converter output

quantisation error

the error from converting an infinitely graded signal to a digital one with finite steps

ideal greatest quantisation error

one half of the step width or half of one least significant bit equivalent on the voltage scale

how to reduce quantisation error

* step width can be narrowed by increasing the number of bits in the ADC process
* however increases complexity, cost and time

sampling frequency

when performing an ADC a sample is taken of the analogue signal and quantised to the accuracy defined by the resolution of the ADC, generally done at the sampling frequency

Nyquist frequency

the sampling frequency must be at least double that of the highest frequency component of the signal

sample and hold

since a conversion take a finite time the input must stay steady during this time

V1 > Vref

Vout = Vdd

V1 < Vref

Vout = Vss

flash

* resistor chain provides a ladder of reference voltages
* one comparator on each rung of the ladder
* some logic to turn the outputs into binary
* very fast
* for n-bits requires (2^n)-1

successive approximation

* make successive guesses
* use a DAC from your guessed digital code
* use a comparator to tell you if guess is too high or low
* adjust accordingly
* for n-bits requires n guesses

crosstalk

* where many channels are sent through one ADC there may be an influence of one on the others
* common problem on cheap multichannel digitisers

pulse width modulation

simple method of using rectangular digital waveform to control an analogue variable

duty cycle

pulse on time (t_on)/pulse period (T)

PWM waveform average

* Vref \* duty cycle/100
* eg 3.3V\*0.2 = 0.66V

how to extract an average value from a PWM signal

use a low pass filter

period to use for a lightbulb

100Hz

period to use for a motor

10x - 100x the revs per second

transistor usages

* need to drive an element with a high voltage
* need to drive an inductive or capacitive element

gate resistor for transistor

to limit the current that comes out of the MCU and it typically a few hundred ohms

transistor with a capacitor

transistor with a diode

transistor with a resistor

timer

some circuit to measure time and so initiate an even when a certain time has elapsed

interrupt

a method that allows a program to be suspended so that the CPU can deal with a certain occurrence and once this has been dealt with the original program can continue to execute as required

tasks

distinct activities that are performed each of which has a block of code that is executed

software polling

the computer is in charge and checks for action when it sees fit

interrupt driven

the hardware is in charge and tells the program that something needs to be done

polling disadvantages

* central processor cannot perform any other tasks during a polling routine
* all inputs are treated equally so a response to an urgent event may be delayed until a relatively insignificant number of potential inputs are screened

stack

* place in RAM
* holds a copy of the program counter (where program left off)
* holds copies of the CPU registers
* stack pointer set to where all this stuff went so it can be retrieved later

interruption vector

points to the location of the interrupted service routine

fixed interruption vector

have highest priority for when things go wrong with the MCU

interrupt mechanisms

* interrupts can be prioritised
* interrupts can be masked (switched off if not needed)
* interrupts can be nested

why can interrupts be bad for data?

extended state of system may be changed by ISR code so have to ensure code it written such that all data and resources will be uncorrupted on return

interrupt service routine good practice

* should not change or interfere with too much memory
* will respond to a new input but only needs to set a flag telling the main program that a new input is waiting
* should execute as fast as possible so make it short

when should interrupts be used?

for infrequent events (1000s of clock cycles), if more infrequent polling should be used

simple timer

* digital counter consisting of a string of flip flops will count up in binary
* can load a start number to initialise the flip flops
* can read the binary output
* can just wait until it has counted all the way to its max

what does clock speed give us?

time resolution

number of bit in flip-flop gives us?

maximum interval

timer polling

* program can set a timer and continuously check if it has reached a given value
* when it has it can run scheduled code

timeout polling

* program can set a timer and when it has elapsed it will run our code
* timeout does not need polling
* can do things in the meantime

system tick timer

* used by the ticker function
* used to call a repeated interrupt
* ensure sampling the ADC at regular intervals
* be careful not to call faster than the time it takes to run the code

task scheduling

* if you use a timer the code must execute faster than the interval between the timer events
* best not to have polling in these since it may overrun its time

synchronous serial communication

transmit a clock signal alongside the data with one clock pulse for each bit of data

master

initiates transmission

slave

receives/transmits when told

serial link SPI

* assume the shift registers in master and slave are 8-bit
* each register is loaded with a new word via parallel I/O lines
* master then produces 8 clock pulses
* for each clock pulse data is output from the MSB of each register (serial data out)
* each SDO is connected to the LSB of the other shift register (serial data in)
* as each bit is clocked out of one register it is clocked into the other
* after 8 clock cycles the word that was in the master shift register has been transferred to the slave shift register and vice versa

serial peripheral interface (SPI)

* bus operates with the master/slave configuration
* is a synchronous serial data communication protocol
* is reasonably fast
* no address, control or acknowledgements sent

how does a master device start an SPI transfer

* configures the SPI clock (SCLK) to be a frequency that the recipient slave device can handle
* sets the chip select line (CS) of the intended recipient to 0V
* starts the clock pulses on SCLK to indicate that that data is to be transferred
* simultaneously sends data as consecutive bits on MOSI
* number of bits in each data frame can be configured but is usually between 4 and 16 bits
* slave returns data in the same manner on MISO

where is SPI used?

* applications with data streaming
* chips and modules that usually sit on the same PCB or are at least in the same instrument
* short distances where the clock and data lines are well controlled
* many peripheral chips have this ‘legacy’ standard interface as it is simple

SPI advantages

* full duplex communication
* higher throughput
* complete protocol flexibility for the bits transferred
* not limited to 8-bit words
* slaves don’t need unique addresses

SPI disadvantages

* no in-band addressing
* no hardware flow control
* no hardware slave acknowledgement
* supports only one master device
* only handles short distances

SPI simple link

* SPI protocol with just 3 wires
* serial clock
* master data output/slave data input
* master data input/slave data output
* only for a single slave
* not all slaves accept the SS being low all the time, some require a high low transition to start them off

SPI with chip select

* SPI protocol with 4 signal wires
* master data output/slave data input
* master data input/slave data output
* slave chip select (usually active low)
* when multiple slave devices exist the master must output a unique chip select signal for each slave
* for n slaves we need (3+n) cables

clock polarity (CPOL)

* CPOL = 0 is actively high
* it is normally low when no transmission
* when active it goes high for each bit
* CPOL =1 is actively low
* it is normally high when no transmission
* when active is goes low for each bit

inter-integrated circuit bus (I2C)

* uses only 2 wires
* data can only be transmitted in one direction at a time (half duplex)

I2C protocol

* each peripheral is known as a node and can act as either a master of a slave
* master controls the data transfer and generates the clock signal
* slave is any device addressed by the master
* more than one microcontroller can be connected to the bus and they can claim the master role at different times
* all data is transferred in block of 8-bits (1 byte)
* each byte is followed by a 1 bit acknowledgement from the receiver

I2C start condition

defined by a high-to-low transition of SDA when SCL is high

I2C stop condition

defined by a low-to-high transition of SDA while SCL is high