Instruction Cycle

Fetch

The FETCH phase obtains the next instruction from memory and loads it into

the instruction register (IR) of the control unit.

The central idea in the von Neumann model is that the program and data both reside in

Memory

Fetch Steps

1. MAR <= (PC)

2. PC <= (PC) + 1

3. MDR <= (MAR)

4. IR <= (MDR)

Decode

The opcode, IR[15:12], is input to the controller (Finite State Machine),which selects the appropriate trajectory to take through the FSM,corresponding to the instruction.

The remaining 12 bits, IR[11:0], are used to set up the data path accordingto the needs of the particular instruction

Evaluate Address

This phase computes the address of the memory location that is needed to process the instruction. LD needs to access memory to load the data into the DR but ADD doesn't need to access memory.

FETCH OPERANDS

This phase obtains the source operands needed to process the instruction.

Opcodes

what the instruction does

operands

who it does it to! like immediate, registers and offsets.

EXECUTE

This phase carries out the execution of the instruction.

STORE RESULT

If there is a result from the operation it is written to memory (using the EA), or to a register.