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CPU
Central Processing Unit; executes instructions and processes data
Von Neumann Architecture
System where data and instructions share the same memory
Input → CPU → Output
Basic data flow in a computer system
CPU Components
Control Unit (CU), Arithmetic Logic Unit (ALU), Registers
Control Unit (CU)
Manages and coordinates CPU operations and sends control signals
Control Unit role
Fetches, decodes, and executes instructions
Control Unit interrupts
Handles hardware interrupts from other devices
Control Unit importance
Considered the “powerhouse” managing CPU processes
Arithmetic Logic Unit (ALU)
Performs arithmetic and logical operations on data
ALU arithmetic operations
Addition, subtraction (and other calculations)
ALU logic operations
AND, OR, NOT
ALU comparisons
Can compare numbers against 0
ALU equality check
Can test if two numbers are equal
ALU implementation
Uses logic gates combined to perform operations
Registers
Small, extremely fast storage locations inside CPU
Register speed
Faster than RAM
Instruction Register (IR)
Holds the current instruction being executed
Program Counter (PC)
Stores the address of the next instruction
Accumulator
Stores results of ALU operations
General Purpose Registers
Temporary storage for data being processed
Clock
Synchronises CPU operations
Clock speed
Measured in Hertz (Hz), cycles per second
1 Hz
One cycle per second
500 Hz
500 cycles per second
3 GHz
3 billion cycles per second
Clock tick
One cycle allowing part of the fetch-decode-execute cycle
Higher clock speed
More instructions processed per second
Pipelining
Technique where multiple instructions are processed simultaneously
Pipelining benefit
Keeps CPU components busy, improves performance
Pipeline condition
If one instruction is fetched every clock cycle
Bus
Pathway connecting CPU to other components
Bus function
Transfers data, addresses, and control signals
Data Bus
Transfers actual data between components
Data bus direction
Bi-directional
Data bus purpose
Used for both reading and writing data
Control Bus
Carries control and status signals
Control bus direction
Bi-directional
Control bus role
Sends commands and receives status signals
Address Bus
Carries memory addresses
Address bus direction
Uni-directional
Address bus purpose
CPU specifies location in memory or device
Address bus size
Determines maximum memory addressable
RAM
Random Access Memory; primary storage
Primary storage
Located close to CPU for fast access
RAM type
Volatile memory
Volatile memory
Data lost when power is off
RAM purpose
Stores currently running programs and data
Secondary Storage
Long-term storage for data
Purpose
Retains data when power is off
Requirement
Must allow data retrieval after restart
Storage Types
Magnetic, Optical, Solid State
Magnetic storage
Uses magnetised material to store data
How it works (magnetic)
Magnetises regions as north/south poles
Binary representation (magnetic)
North/South = 1s and 0s
Examples (magnetic)
Hard disk drive (HDD), Magnetic tape
Magnetic advantages
High capacity, low cost per GB, moderate speed
Magnetic disadvantages
Easily damaged, heavy, prone to mechanical failure
Optical storage
Uses laser to read/write data on reflective surface
Structure (optical)
Flat disc with reflective layer
Pits and lands
Pits = burned areas, Lands = unburned areas
Binary interpretation (optical)
Reflection = land, no reflection = pit
Examples (optical)
DVD, CD
Optical advantages
Low cost, no physical contact, portable, silent
Optical disadvantages
Very low capacity, slow speeds, prone to scratches
Solid state storage
Uses NAND flash memory (no moving parts)
Material (SSD)
Silicon chips
How it works (SSD)
Electrons trapped in “pools”
Binary representation (SSD)
Full pool = 0, empty pool = 1
Examples (SSD)
SSD, USB flash drive
Solid state advantages
Fast read/write, durable, portable, silent
Solid state disadvantages
High cost per GB, limited write cycles
Primary vs Secondary Storage
RAM is volatile; secondary storage is permanent
Register vs RAM
Registers are faster but much smaller
Clock speed vs performance
Higher speed = more cycles = faster processing
Address bus vs memory
Wider bus = more memory accessible
Pipelining impact
Improves throughput, not necessarily single instruction speed