Processor Structure/Processor

function of ALU

completes arithmetical and logical operations

• addition/subtraction on fixed/floating point binary

• logic operations

function of control unit

directs operations of CPU

• controls/coordinates activities of CPU

• manages flow of data between CPU and other devices

• accepts next instruction

• decodes instructions

• stores resulting data back in memory

functions of registers

small memory cells that operate at high speeds to temporarily store data and perform arithmetic, logical and shift operations

function of program counter

holds the address of the next instruction to be executed

function of accumulator

stores the results from calculations

function of memory address register

holds address of location that is to be read from or written to

function of memory data register

temporarily stores data that has been read or needs writing to

function of current instruction register

holds current instruction being executed, instruction is divided into operand and opcode

what is a bus

set of parallel wires which connect two or more components inside CPU

• width of bus = no. of parallel wires it has

  • directly proportional to number of bits that can be transferred simultaneously at a given time

what does the data bus do

transports data and instructions between components

• bi-directional

what does the address bus do

transmits memory addresses specifying where data is to be sent/retrieved

• width is proportional to no. of addressbale memory locations

what does the control bus do

transmits control signals between internal and external components

• bi-directional

• coordinates use of address/data buses

  • provides status information between system components

state and explain the 6 control signals

bus request - shows a device is requesting use of data bus

bus grant - shows CPU has granted access to data bus

memory write - data is written into addressed location using bus

memory read - data is read from specific location to be placed onto data bus

interrupt request - shows a device is requesting CPU access

clock - used to synchronise operations

what is assembly language

uses mnemonics to represent instructions

• simplified way of representing machine code

• instruction divided into operand and opcode in CIR, operand = data/address of data of which the operation is to be performed, opcode = type of instruction

what is pipelining and how does it work

process of completing FDE cycle simultaneously

• each instruction is at a different stage of FDE cycle

what are the pros and cons of pipelining

pros:

• reduces time taken for instruction to go through FDE

• faster speed as CPU is not idle while waiting for next instruction

cons:

• if there is a branch in program, pipeline is flushed (jumping over parts of code for pipelining)

describe ad explain the FDE cycle

1. Address from PC is copied to MAR

2. Instruction held at that address is copied to MDR via data bus

3. Simultaneously contents of PC are incremented by 1

4. Value held in MDR is copied to CIR

5. Contents of CIR are split into opcode and operand

6. This is decoded then executed

What are the 3 factors affecting CPU performance

Clock speed, number of core, cache

What is clock speed and how does it affect CPU performance

Frequency at which internal clock generates pulse

• changed from 1 to 0 and vice verse

• higher the clock rate, faster the computer works as more instructions executed per second

What is a core and how does it affect CPU performance

Processor in CPU

• if a computer has 2 cores, it can perform 2 instructions simultaneously

• each core runs as same speed

• the more cores, the faster tasks can be carried out

why isn’t a dual core 2x faster than 1 core

• time spent organising tasks between cores

• not all software’s can optimise depending on cores

what is cache and how does it affect CPU performance

main store between central processor and rest off memory

• extremely fast access as closer to CPU than RAM

• instructions fetched from main memory are copied to cache to be accessed if needed again

• part of primary storage

• the more cache, the more data can be stored

what are the 3 levels of cache

level 1

• very fast memory cells with small capacity

level 2

• relatively fast memory cell with medium sized capacity

level 3

• much larger and slower memory cell

describe and explain von neumann architecture

• has basic components of computer/processor

  • CU, ALU, registers, cache

• shared memory and shared data bus used for both data and instructions

describe and explain harvard architecture

• physically separate memories for instructions and data

  • useful for when memories have different characteristics

compare harvard and von neumann architecures

von neumann:

• unified memory, single bus, shared address space, single CU

• cheaper to develop and CU is easier to design

• programs can be optimised in size

  • used in modern computers

harvard:

• separated memroy, separate buses, distinct address spaces, separate CU’s

• quick execution as data and instructions can be fetched in parallel

• memories can be different sizes = more efficient use of space

  • used in specialise embedded systems