Computer Architecture - CPU Structure & Instruction

These flashcards cover essential concepts from the lecture on CPU structure, instruction cycle, and pipelining in computer architecture.

What are the key components of CPU organization?

Control Unit, Arithmetic Logic Unit (ALU), Memory Unit (MU).

What is the instruction cycle also known as?

The fetch-execute cycle.

What is pipelining in computer architecture?

A technique where multiple instruction stages are processed in parallel to improve CPU performance.

What are the three main types of processors?

Single Core, Dual-Core, Quad-Core Processors.

Why are pipeline hazards significant in CPU performance?

They disrupt the smooth execution of the instruction pipeline.

What limitations do data hazards impose in pipelining?

They occur when an instruction depends on the result of a previous instruction.

What does RISC stand for?

Reduced Instruction Set Computer.

What is the benefit of instruction pipelining?

It allows for quicker execution time of a large number of instructions.

What happens during the Fetch Decode Execute cycle?

An instruction is fetched from memory, decoded, and then executed.

What are structural hazards in pipelining?

They occur when two instructions need to access the same resource.

What is CPU Organization?

It refers to the structure and functioning of the CPU, focusing on how internal components like the ALU, Control Unit, and registers are arranged to perform tasks.

Define Instruction Pipelining.

A technique where the microprocessor begins executing a second instruction before the first one is completed, performing stages in parallel.

In the "Laundry Analogy," what determines the finish time of the entire process?

The slowest stage in the pipeline.

Does pipelining speed up the execution time of a single individual task?

No; the individual task still takes the same amount of time, but the average execution time for many tasks is reduced .

What is a "Data Hazard"?

A situation where an instruction depends on the result of a previous instruction that has not yet been written back to the registers.

What does RISC stand for, and what is its memory philosophy?

Reduced Instruction Set Computer; only "load" and "store" operations are allowed to affect memory.

In RISC architecture, where do all operations on data typically apply?

Data must be in registers, and operations usually change the entire register (e.g., 32 or 64 bits).

What is the purpose of the "Decode" stage?

The instruction is sent to the Control Unit to identify the specific Opcode and Operand.

What is a Quad-Core processor?

A chip containing four independent cores (essentially two dual-core processors on one IC) that read and execute instructions to increase program speed .