Sequential Logic Design - Controllers

This set of flashcards covers key vocabulary and concepts discussed in the lecture on sequential logic design and controllers.

Sequential Circuit

A circuit where the output depends not just on the present inputs but also on the past sequence of inputs.

SR Latch

A basic storage element that can store one bit, set by S and reset by R.

D Latch

A level-sensitive device that captures the value of D when C is high and retains it when C is low.

D Flip-Flop

An edge-triggered device that stores the value of D only on the rising edge of the clock signal.

Finite-State Machine (FSM)

A mathematical model of computation consisting of states, transitions, inputs, and outputs.

Race Condition

An undesirable situation where a signal's value oscillates due to simultaneous inputs, causing unpredictable behavior.

Metastability

A condition where a circuit's output is uncertain due to timing margins, leading to unreliable states.

Glitches

Unwanted pulses or transitions caused by propagation delays in the circuit.

Boolean Equations

Mathematical formulas that describe the behavior of digital circuits in terms of logical variables.

Timing Diagrams

Graphical representations of the changes in signal states over time, used to analyze the behavior of sequential circuits.