Computer Organisation and Architecture

What are the main internal hardware components of a computer system? (AQA list)

Processor (CPU); main memory (RAM/ROM); address bus; data bus; control bus; I/O controllers; these are the components specified in the AQA spec that you must know the roles and relationships of

What is the role of the processor (CPU)?

Executes program instructions stored in main memory; fetches, decodes and executes instructions using the fetch-execute cycle; contains the ALU, CU, registers, and clock; the "brain" of the computer

What is main memory and what does it store?

Directly addressable memory connected to the CPU via buses; stores currently executing program instructions and data; includes RAM (volatile, read/write) and ROM (non-volatile, read-only for firmware); much faster than secondary storage but smaller capacity

What is the address bus?

A unidirectional bus carrying memory addresses from the CPU to memory/I/O controllers; the width (number of lines) determines the maximum addressable memory; e.g. 32-bit address bus → 2³² = 4 GiB addressable memory

What is the data bus?

A bidirectional bus carrying data between the CPU, memory, and I/O controllers; width determines how much data can be transferred per cycle (word size); e.g. 64-bit data bus transfers 8 bytes per clock cycle

What is the control bus?

A bidirectional collection of individual control lines that coordinate and manage data transfer across the system bus; carries signals such as: memory read, memory write, clock signal, interrupt request, bus request/grant, reset

What is an I/O controller?

An interface between the CPU/buses and peripheral devices; converts signals between the CPU's bus protocol and the device's own protocol; each peripheral type has its own controller (e.g. disk controller, USB controller); managed by the OS via device drivers

What is the von Neumann architecture?

A computer architecture where programs and data are stored together in the same memory space; a single bus connects CPU and memory; instructions fetched and executed sequentially; basis of most general-purpose computers; bottleneck: the von Neumann bottleneck (single bus limits data transfer speed)

What is the Harvard architecture?

A computer architecture where program instructions and data are stored in physically separate memory with separate buses; the CPU can fetch an instruction AND read/write data simultaneously; used in embedded systems and DSP processors; faster for specific tasks but more complex hardware

Compare von Neumann and Harvard architectures

Von Neumann: single shared memory for instructions and data; simpler design; flexible (can treat data as instructions); general-purpose computers; limited by von Neumann bottleneck. Harvard: separate instruction/data memory and buses; faster — simultaneous instruction fetch and data access; used in embedded/DSP systems; less flexible; more complex hardware

What is the stored program concept?

The principle that machine code instructions are stored in main memory and fetched and executed serially by a processor; both programs and data are stored as binary in the same memory; enables general-purpose computing — programs can be changed by altering memory contents without rewiring hardware

What is the Arithmetic Logic Unit (ALU)?

The component of the CPU that performs all arithmetic operations (addition, subtraction, multiplication) and logical/bitwise operations (AND, OR, NOT, XOR, comparisons, shifts); produces a result and sets flags in the status register

What is the Control Unit (CU)?

The component of the CPU that coordinates the operation of all other components; fetches instructions from memory, decodes them, and sends control signals to execute them; manages the fetch-execute cycle; does not process data itself

What is the clock?

An electronic oscillator that generates a regular square wave signal; each rising edge (tick) triggers one step of the CPU's operation; the clock speed (measured in Hz/GHz) determines how many operations per second the CPU can perform

What is the Program Counter (PC)?

A dedicated register that holds the memory address of the NEXT instruction to be fetched; automatically incremented after each fetch; modified by branch instructions (conditional/unconditional jumps)

What is the Current Instruction Register (CIR)?

A dedicated register that holds the instruction currently being decoded and executed; the instruction is fetched from memory into the CIR at the start of each fetch-execute cycle

What is the Memory Address Register (MAR)?

A dedicated register that holds the memory address to be accessed (read or written); connected to the address bus; the address is placed in the MAR before a memory access is initiated

What is the Memory Buffer Register (MBR) / Memory Data Register (MDR)?

A dedicated register that temporarily holds data being read from or written to memory; acts as a buffer between the CPU and main memory; connected to the data bus

What is the Status Register?

A dedicated register containing individual flag bits that record the outcome of operations; common flags: Zero (Z) — result is zero; Carry (C) — arithmetic carry/borrow occurred; Negative (N) — result is negative; Overflow (V) — signed overflow occurred; used by conditional branch instructions

What are general-purpose registers?

Registers within the CPU used to store temporary data, operands, and results during instruction execution; their use is determined by the programmer/compiler; e.g. R0–R15 in ARM architecture

Describe the Fetch stage of the fetch-execute cycle

(1) Contents of PC copied to MAR via address bus; (2) Memory read control signal sent; (3) Instruction at address in MAR copied into MBR via data bus; (4) Contents of MBR copied into CIR; (5) PC incremented to address of next instruction

Describe the Decode stage of the fetch-execute cycle

The CU decodes the instruction in the CIR; splits the instruction into opcode (operation to perform) and operand(s) (data/address); determines what action is needed and which resources to use

Describe the Execute stage of the fetch-execute cycle

The CU sends control signals to the appropriate components; e.g. ALU performs arithmetic/logic; data loaded from memory into registers; result stored back to memory or register; if a branch instruction: PC updated with new address

PRACTICE: Trace the fetch-execute cycle for the instruction LDA 50 (load accumulator from address 50) stored at address 100

Fetch: PC=100 → MAR=100; memory read → MBR=LDA 50; CIR=LDA 50; PC=101. Decode: CU decodes opcode=LDA, operand=50. Execute: MAR=50; memory read → MBR=contents of address 50; accumulator/register = MBR

What is an instruction set?

The complete set of machine code instructions that a particular processor can execute; each processor has its own unique instruction set (ISA — Instruction Set Architecture); programs must be compiled for the specific ISA of the target processor

What does an instruction consist of?

An opcode and one or more operands; the opcode specifies the operation to perform; the operand specifies the data or address involved; the number of bits allocated to each field depends on the instruction format

What is immediate addressing mode?

The operand IS the actual data value to be used; e.g. LDR R0, #5 loads the value 5 into R0; fast — no additional memory access needed; limited to small values that fit in the operand field

What is direct addressing mode?

The operand contains the memory address where the data is stored; the CPU must access that memory address to retrieve the actual data; e.g. LDR R0, 100 loads the value stored at memory address 100 into R0

PRACTICE: Explain the difference between LDR R0, #42 and LDR R0, 42

LDR R0, #42 uses immediate addressing — the value 42 is loaded directly into R0; LDR R0, 42 uses direct addressing — the value stored at memory address 42 is loaded into R0; the operand in direct addressing is an address not a value

State the machine code operations AQA requires you to know

LDR/LOAD (load register from memory); STR/STORE (store register to memory); ADD (add); SUB (subtract); MOV (move/copy value); CMP (compare — sets flags, no stored result); B (unconditional branch); B[condition] (conditional branch e.g. BEQ, BNE, BGT); AND/OR/NOT/XOR (logical bitwise); LSL (logical shift left); LSR (logical shift right); HALT (stop execution)

What does a logical shift left by n positions do to a binary value?

Shifts all bits n positions to the left; vacated positions filled with 0s; bits shifted off the left end are lost; equivalent to multiplying by 2ⁿ (for unsigned values, providing no significant bits are lost)

What does a logical shift right by n positions do?

Shifts all bits n positions to the right; vacated positions filled with 0s; bits shifted off the right end are lost; equivalent to integer division by 2ⁿ

PRACTICE: Apply LSL 2 to 00010110 (22₁₀)

00010110 → shift left 2 → 01011000 = 88₁₀ = 22 × 4 ✓

PRACTICE: Write assembly language to add the values at addresses 200 and 201 and store result at address 202

LDR R0, 200; LDR R1, 201; ADD R2, R0, R1; STR R2, 202

What is the effect of multiple cores on processor performance?

Each core can independently fetch and execute instructions; multiple cores allow genuine parallel execution of different processes/threads simultaneously; performance improvement depends on whether software is written to utilise multiple cores (multi-threading); does not improve single-threaded performance

What is cache memory and how does it improve performance?

Small, very fast SRAM memory built into/near the CPU; stores recently accessed or frequently used instructions and data; exploits temporal and spatial locality; when the CPU needs data it checks cache first (cache hit) before slower RAM (cache miss); reduces average memory access time significantly

What are the levels of cache (L1, L2, L3)?

L1: smallest (KB), fastest, closest to CPU core, lowest latency; L2: larger (MB), slightly slower; L3: largest (several MB), slowest of the caches but still much faster than RAM; data not found in L1 checked in L2, then L3, then RAM

How does clock speed affect processor performance?

Higher clock speed (Hz) = more fetch-execute cycles per second = faster instruction execution; measured in GHz; however, higher clock speeds generate more heat and consume more power; performance also depends on IPC (instructions per cycle)

What is word length and how does it affect performance?

The number of bits processed as a single unit by the CPU in one operation; larger word length (e.g. 64-bit vs 32-bit) allows larger numbers to be processed in a single instruction; allows more data per bus transfer; 64-bit processors can address far more memory (2⁶⁴ bytes) than 32-bit (2³² = 4 GiB)

How does address bus width affect performance?

Wider address bus = more unique memory addresses = larger addressable memory space; e.g. 32-bit address bus → max 4 GiB RAM; 64-bit → vastly more; does not directly affect speed but prevents memory limitation bottlenecks

How does data bus width affect performance?

Wider data bus = more data transferred per clock cycle between CPU and memory; reduces the number of separate transfers needed for large data values; directly increases memory bandwidth

PRACTICE: Explain why increasing cache memory size may improve performance more than increasing clock speed

Increasing cache reduces cache miss rate, meaning more data is served from fast cache rather than slow RAM; memory access latency is often the bottleneck (von Neumann bottleneck), not raw processing speed; increasing clock speed only helps if the processor isn't already waiting for memory; larger cache directly addresses the memory bottleneck whereas faster clock speed has diminishing returns if memory is the limiting factor

Name the four input/output and storage devices AQA requires for principles of operation

Input/output: barcode reader, digital camera, laser printer, RFID; Secondary storage: hard disk (HDD), optical disk, solid-state disk (SSD)

How does a barcode reader work?

A light source (laser or LED) illuminates the barcode; a photodetector measures reflected light intensity; white bars reflect more light, black bars absorb more; the pattern of light/dark reflections is converted to binary digits representing the encoded data; processed to decode the product information

How does a digital camera work?

Light passes through a lens and is focused onto a CCD (charge-coupled device) or CMOS sensor; the sensor contains millions of photosensitive pixels; each pixel generates an electrical charge proportional to the light intensity hitting it; the charge is converted to a digital value (ADC); the resulting grid of values forms the digital image; colour captured using a Bayer filter (RGB filter array over sensor pixels)

How does a laser printer work?

(1) A laser beam deflected by a rotating mirror scans across a charged photosensitive drum; (2) where the laser hits, the charge is discharged (forms the image); (3) toner (fine charged powder) adheres to discharged areas; (4) paper is given opposite charge and passed close to the drum — toner transfers to paper; (5) fuser unit uses heat and pressure to permanently bond toner to paper

How does RFID work?

A reader emits radio frequency electromagnetic waves; an RFID tag (which may be passive — no battery) uses electromagnetic induction to power itself from the reader's field; the tag's antenna and chip send back a unique identifier; used for contactless payment, access control, stock management, passports

How does a hard disk drive (HDD) work?

Magnetic disk platters rotate at high speed (e.g. 7200 RPM); read/write heads float nanometres above the platter surface; data stored as patterns of magnetic polarisation on tracks divided into sectors; heads move radially across platters (seek time + rotational latency = access time); high capacity, moderate speed, mechanical — vulnerable to physical shock

How does an optical disk work?

A laser diode reads/writes data by detecting/creating microscopic pits and lands on a reflective disc surface; pits reflect less light than lands; transitions between pit/land represent 1s; same surface = 0s; types: CD (700 MB), DVD (4.7–17 GB), Blu-ray (25–50 GB per layer); read-only or recordable (R/RW) variants

How does a Solid State Drive (SSD) work?

Uses NAND flash memory: floating gate transistors store charge to represent data; organised into pages (smallest read/write unit) grouped into blocks (smallest erasable unit); pages cannot be overwritten directly — the block must be erased first then rewritten; a controller manages this complexity; no moving parts → lower latency, faster access, more robust; higher cost per GB than HDD

Compare HDD, optical disk, and SSD for capacity, speed, and suitability

HDD: high capacity (TB), moderate speed, low cost/GB, mechanical, suitable for bulk storage; Optical: lower capacity (GB), slow, cheap per disk, removable, suitable for distribution/archiving; SSD: high capacity (TB), very fast (low latency), no moving parts, expensive per GB, suitable for OS/applications requiring fast access

PRACTICE: Explain why SSDs have faster access times than HDDs

HDDs require mechanical movement — the read/write head must physically seek to the correct track (seek time) and wait for the correct sector to rotate under the head (rotational latency); SSDs have no moving parts — data is accessed electronically with no mechanical delay; SSD latency is typically microseconds vs milliseconds for HDD

PRACTICE: A student claims SSDs cannot overwrite data. Evaluate this claim.

Partially correct: SSDs cannot directly overwrite data at the page level; the entire block containing the page must first be erased before new data can be written (because writing requires cells to be in the erased/uncharged state); the SSD controller manages this using garbage collection and wear levelling to minimise the performance impact; from the user's perspective data appears to be overwritten normally, but internally the process is erase-then-write at block level