Synchronous Circuits

By using combinational logic and one or more flip-flops.

How are the Synchronous sequential circuits realized?

Stored values in the flip-flop

Controlled by the clock signal

which changes the state of the flip-flop.

The circuit moves from one state to another, ensuring only one transition per clock cycle.

Sources are primary inputs and the flip-flop’s current state.

FSM: Finite State Machine

A formal name for a sequential circuit. Its behavior can be represented with a finite number of states. Used to control physical systems.

Designing a State Diagram

States and transitions are represented pictorially as nodes and arcs. Each state has defined outputs and transitions based on inputs.

Node / (Start State)

Starting state of FSM. Output is always 0. Arcs show transitions depending on input conditions, returning to itself or moving to another state.

Node / (Intermediate State)

Transition state where output remains 0. Has arcs that loop back or move to another state depending on inputs.

Node / (Output State)

Output is 1 in this state. Circuit stays here if inputs persist, or returns to a prior state if inputs reset.

State variables

Represent present-state variables of flip-flops. Used to track FSM states.

Next-state variables

Combinational circuit’s outputs; determine how flip-flops update their state at each active clock edge.

Z = (Output Expression)

Output depends only on present state variables. Circuit determined to be Moore type

D Flip-Flops

Used when next-state variables directly become the new state values. Simplifies FSM implementation.

Resetn Input

Active-low input clears flip-flops to zero, forcing FSM into a known initial state.

Improved Circuit Version

Uses fewer gates, leading to reduced cost and simpler design.

Timing Diagram

Shows when signals change with respect to clock edges, including propagation delays through flip-flops.

Sequence Detectors

Circuits designed to detect a specific sequence of input symbols.

One-Hot State Diagram

Each state assigned a unique binary valuation where only one bit is high. Simplifies expressions but requires more flip-flops.

Data Transfer Control Circuit

Moves data between registers using a temporary register, ensuring correct swapping of values.

Data Transfer State A

No transfer occurs; all outputs are 0.

Data Transfer State B

Contents of R2 are moved to R3; circuit then advances.

Data Transfer State C

Contents of R1 are moved to R2; circuit then advances.

Data Transfer State D

Contents of R3 are moved to R1, completing the swap.

Output Signal Done

Asserted in the final state to indicate completion of the transfer.

Flip-Flop Choice for Data Transfer Circuit

D flip-flops are used, simplifying state representation and transitions.

One-Hot Encoding (Data Transfer)

Assigns one flip-flop per state, making output expressions simpler but requiring more hardware.

Mealy Type FSM (First Example)

Output depends on both inputs and present state. Requires fewer states than Moore but reacts immediately to inputs.

Moore Type FSM (First Example)

Output depends only on the present state. Requires an additional clock cycle before output changes.

Mealy FSM Timing Diagram

Output responds immediately to input, unlike Moore which has a one-cycle delay.

Moore FSM Timing Diagram

Output changes only after a state transition, causing a delay.

Mealy vs Moore Circuits

Mealy circuits are generally simpler and faster but may be less stable; Moore circuits are more predictable but need more states.

Data Transfer Control (Mealy Type)

Achieves the same swap function in fewer states but still requires two flip-flops.

One-Hot Mealy FSM

Uses three flip-flops for three states. Simplifies logic at the cost of more hardware.

Serial Adder

Adds numbers one bit at a time. Cheaper but slower than parallel adders.

FSM Adder (Serial Adder)

FSM controls addition of bit pairs with carry. Requires state tracking.

Shift Registers in Serial Adder

Hold operands and sum during computation. Provide bits sequentially at each clock cycle.

Carry States in Serial Adder FSM

Two states (carry = 0 and carry = 1) track whether a carry exists from the previous addition.

State G (Carry = 0)

Computes sum without carry. Remains in same state unless carry generated.

State H (Carry = 1)

Computes sum including carry. Returns to G if no new carry is generated.

FSM State Table (Serial Adder)

Defines transitions between carry states depending on input bits.

Serial Adder Flip-Flop Requirement

Only one flip-flop is needed to represent the two carry states.

Moore Serial Adder FSM

Requires more states because outputs depend only on the FSM state, not inputs.

State Splitting in Moore FSM

Splits states based on both carry and sum outputs, increasing number of states.

Sum Output in Moore FSM

Determined only by state variables, not direct inputs.

Carry Output in Moore FSM

Also derived from state variables, requiring extra states compared to Mealy version.

Moore Serial Adder Output Delay

Output delayed by one clock cycle due to extra flip-flop used in state machine.

Simple FSM (3 States A, B, C) – Moore Implementation

module simple(CLK, RSTn, W, Z);

input CLK, RSTn, W;

output reg Z;

reg [1:0] y, Y;

parameter A = 2'b00, B = 2'b01, C = 2'b10;

always @(*) begin

case (y)

A: if (W) Y = B; else Y = A;

B: if (W) Y = C; else Y = A;

C: if (W) Y = C; else Y = A;

default: Y = A;

endcase

end

always @(negedge RSTn or posedge CLK) begin

if (!RSTn) y <= A;

else y <= Y;

end

always @(*) Z = (y == C);

endmodule

Mealy FSM (2 States A, B) – Sequence Detector

module mealy(CLK, RSTn, W, Z);

input CLK, RSTn, W;

output reg Z;

reg y, Y;

parameter A = 1'b0, B = 1'b1;

always @(*) begin

case (y)

A: begin

Z = 0;

if (W) Y = B; else Y = A;

end

B: begin

if (W) begin Z = 1; Y = B; end

else begin Z = 0; Y = A; end

end

endcase

end

always @(negedge RSTn or posedge CLK) begin

if (!RSTn) y <= A;

else y <= Y;

end

endmodule