1.1.1 structure and function of the processor

arithmetic logic unit

completes all the arithmetical and logical operations

the control unit

a part of the processor which directs operations inside the CPU

registers

small memory cells that operate at high speeds

where do all the arithmetic, logic or shift operations occur

in registers

program counter

holds the address of the next instruction

where are the results of the ALU stored

in ACC

memory address register

holds the address of a location that is to be read from or written to

memory data register

temporarily stores the data that has just been read from or the data that needs to be written

current instruction register

holds the current instruction divided up into opcode and operand

bus

a set of parallel wires connecting two or more components together

system bus

the collection of the data bus, address bus and control bus

what is the width of a bus

the number of parallel wires it has

data bus

a bidirectional bus used to transport data and instructions between components

control bus

bi-directional bus used to transmit control signals between internal and external components

address bus

used to transmit the memory address specifying where data is to be sent from or retrieved from

what does adding a wire to the address bus do the the number of addressable locations?

it doubles the number of addressable locations

bus request

indicates a device is requesting access to the data bus

bus grant

indicates the cpu has granted access to the data bus

memory write

causes the data on the data bus to be written into the addressed location

memory read

causes the data from the addressed location to be places onto the data bus

interrupt request - control signal

indicates that a device is requesting access to the cpu

clock control signal

used to synchronise instructions

opcode

used to determine the type of instruction and what hardware to use to execute it

operand

the address of where the operation is preformed

fetch phase

• the address from the pc is copied to the mar

• instruction held at that address is copied to the mar by the data bus, and the PC is incremented by 1

• the contents of the mar is copied to the cir

decode phase

the contents of the CIR is split into operand and opcode

execute phase

the opcode is executed on the data

clock speed

the number of clock cycles completed per second

cache memory

small amount of memory within the CPU that can be accessed a lot faster than main memory

pipelining

the process of carrying out multiple instructions concurrently. Each instruction will be at a different stage of the FDE cycle.

von neumann architecture

in which there is a single shared memory and shared data bus for both data and instructions

harvard architecture

in which there is two seperate memory and data buses for data and instructions

contemporary processing

in which von neumann architecture is used for main memory. cache uses harvard architecture, divided into instruction cache and data cache