Lecture_17-CSCI_U310_01-Jahangir_Majumder-Spring_2025

These flashcards cover key concepts related to memory technology and direct-mapped cache from the CSCI U310 lecture.

What technology is the focus of Lecture 17 in the CSCI U310 class?

Memory Technology.

What is the example memory size given for the direct-mapped cache in the lecture?

16KB.

What type of blocks is used in the direct-mapped cache example discussed?

4 word blocks.

What happens when the cache entry is not valid during a read operation?

The data is loaded into cache, setting the tag and valid bit.

What defines if a cache line is valid or invalid?

Valid bit.

What does the index in a cache address identify?

The cache line where the data is stored.

What is the outcome when there is a cache miss?

The CPU stalls and fetches the block from the next level of memory hierarchy.

What is the result of a cache hit?

The data is retrieved from the cache without needing to access main memory.

What are the three types of cache write operations?

Write-through, write-back, and write misses.

What two caches are mentioned in the three-level cache organization?

Level 1 (L1) cache and Level 2 (L2) cache.

What is the primary storage technology mentioned for main memory?

DRAMs.

What is the result of a cache read operation if the data is not found?

Access main memory for the required data.

What is the miss penalty in bus cycles for fetching 4-word data from DRAM?

65 bus cycles.

Which memory hierarchy levels are involved in the cache read operation?

Cache and main memory.

What should be considered to improve cache performance?

To put the most commonly used data in cache.