Modules 9-10 - Pipelining and MIPS Architecture (Part 2)

Pipelining is a technique used in computer architecture to improve the performance and efficiency of __________.

Processors or central processing units (CPUs).

The first stage in the instruction execution pipeline is __________.

Instruction Fetch.

During the Instruction Fetch stage, the processor performs the steps of __________, __________, and __________.

Program Counter (PC) Update, Instruction Fetch, Increment Program Counter.

The second stage in the instruction execution pipeline is __________.

Instruction Decode.

In the Execute stage, the processor carries out the steps of __________, __________, and __________.

ALU Operation, Operand Calculation, Result Generation.

Memory Access stage follows the __________ stage in the instruction execution pipeline.

Execute.

The final stage in the instruction execution pipeline is __________.

Write Back.

During the Write Back stage, the processor performs the steps of __________, __________, and __________.

Result Availability, Destination Determination, Write Back.

The purpose of the Instruction Decode stage is to decode the instruction and determine the necessary __________.

Operations.

In the Memory Access stage, the processor performs steps such as Memory Address Calculation and __________.

Memory Access.