front and back end design

Chip Specification

Defines functionality, performance, and physical constraints of the chip (e.g., read sensors, 100 MHz, 10mm x 10mm).

Output of Chip Specification

Requirements document describing what the chip must do.

Architecture Definition

Defines CPU structure (RISC/CISC), memory interface, I/O controllers, and communication protocols.

Output of Architecture Definition

High-level block diagrams and subsystem interfaces.

Functional Design

Behavioral description using HDL such as Verilog or VHDL.

Output of Functional Design

Simulated HDL code that matches intended behavior.

Logic Design

Converts HDL into Boolean logic and gate-level circuits (XOR, AND, OR).

Output of Logic Design

Gate-level netlist.

CMOS Inverter (Functional)

Output = NOT(input); implemented as b = ~a in Verilog.

Circuit Design

Transistor-level implementation of logic gates using CMOS.

Output of Circuit Design

Transistor-level schematics with device sizing.

Physical Design

Layout of transistors, routing, standard cells, and DRC/LVS checks.

Output of Physical Design

GDSII layout file ready for fabrication.

Wafer Processing

Creating silicon wafers from melted ingots at ≥1400°C.

Photolithography

Mask-based patterning using light and photoresist.

Steps of Photolithography

Coat → Expose → Develop → Etch → Strip.

Ion Implantation

Adds dopants to form NMOS/PMOS regions and adjust threshold voltage.

Metallization

Adds interconnect layers between devices.

Planarization

Polishes wafer surface to make it flat for additional layers.

Assembly and Packaging

Protects the chip and connects it to the outside world.

Wafer Test

Tests each die before packaging to avoid wasting packages.

Package Test

Final electrical testing after packaging.

NMOS Behavior

Conducts when gate voltage is HIGH.

PMOS Behavior

Conducts when gate voltage is LOW.

CMOS Inverter Pull-Up Device

PMOS pulls output HIGH.

CMOS Inverter Pull-Down Device

NMOS pulls output LOW.

Mead-Conway Methodology

Enabled structured, modular, scalable chip design and modern CAD tools.

Transition to CMOS

Provided low power, fast switching, and high density for VLSI.

Standard Cell Design

Uses reusable layout blocks to speed up physical design.

Deep Submicron Fabrication

Scaling from 180nm to 7nm with advanced lithography and doping precision.

System-on-Chip Integration

Combines CPU, GPU, memory, and I/O on a single chip.