Computer Architecture flashcards

The questions from the quizzes. Will be updated regularly.

Computer Architecture mainly deals with:

 

Physical wiring of the computer

 

Logical structure and functional behavior of a computer system

 

The placement of transistors on a chip

 

Writing software applications

Logical structure and functional behavior of a computer system

The Von Neumann model is primarily based on:

 

Harvard architecture

 

Separate memory for data and instructions

 

Single memory for both data and instructions

 

Multi-core parallel execution

Single memory for both data and instructions

Which component holds the address of the next instruction to be executed?

 

MAR

 

MDR

 

PC

 

IR

PC

Special-purpose registers are designed to:

 

Hold intermediate arithmetic results

 

Perform specific control or memory management tasks

 

Store random program variables

 

Replace general-purpose registers

Perform specific control or memory management tasks

The stack pointer (SP) is used to:

 

Keep track of program loops

 

Store arithmetic results

 

Point to the top of the stack in memory

 

Store base addresses for arrays

Point to the top of the stack in memory

MAR (Memory Address Register) stores:

 

Data fetched from memory

 

Address of the memory location to be accessed

 

Instructions to be executed

 

Control signals

Address of the memory location to be accessed

MDR (Memory Data Register) is used to:

 

Store the program counter

 

Store the current instruction

 

Temporarily hold data read from or written to memory

 

Control program flow

Temporarily hold data read from or written to memory

Which register stores the instruction currently being executed?

 

PC

 

IR

 

MDR

 

MAR

IR

The ALU (Arithmetic Logic Unit) performs:

 

Instruction decoding

 

Memory addressing

 

Arithmetic and logical operations

 

Instruction scheduling

Arithmetic and logical operations

The flag register is mainly used to:

 

Indicate CPU clock rate

 

Record conditions from ALU operations (e.g., zero, carry, overflow)

 

Store immediate operands

 

Control memory mapping

Record conditions from ALU operations (e.g., zero, carry, overflow)

“Hz” in CPU performance represents:

 

Instructions executed per second

 

Clock frequency in cycles per second

 

Memory bandwidth

 

Cache latency

Clock frequency in cycles per second

The “Clock Rate” of a processor refers to:

 

Number of ALU operations per cycle

 

Frequency of the system clock

 

Memory size of the processor

 

Bus transfer rate

Frequency of the system clock

The “Power Wall” in processor design refers to:

 

Limitation of chip manufacturing cost

 

Limit on increasing CPU frequency due to heat and energy consumption

 

Limitation of memory size

 

Maximum achievable instruction throughput

Limit on increasing CPU frequency due to heat and energy consumption

Clock Cycle Time Period is defined as:

 

Time required to fetch one instruction

 

Time taken for one clock tick = 1 / (Clock Frequency)

 

The number of instructions per second

 

Bus transfer time

Time taken for one clock tick = 1 / (Clock Frequency)

The Timing & Control Unit of the CPU:

 

Performs multiplications and additions

 

Manages cache memory

 

Coordinates fetching, decoding, and execution of instructions

 

Stores program instructions

Coordinates fetching, decoding, and execution of instructions

Which of the following is a General-Purpose Register?

 

RA

 

SP

 

PC

 

IR

RA

Types of software include:

 

Application, System, Utility

 

Input, Output, Processing

 

Hardware, Firmware, Kernel

 

Instruction, Execution, Microcode

Application, System, Utility

A compiler is best defined as:

 

A program that converts high-level code into machine code

 

A program that executes code line by line

 

A type of operating system

 

A special-purpose register

A program that converts high-level code into machine code

The instruction cycle begins with:

 

Instruction Decode

 

Instruction Fetch

 

Instruction Execute

 

ALU Operation

Instruction Fetch

During the fetch phase, the CU:

 

Increments the Program Counter (PC)

 

Loads the instruction into IR

 

Sends the PC content to MAR

 

All of the above

All of the above

The decode phase interprets:

 

Control signals

 

The OpCode in the IR

 

Data in the MDR

 

Results in the ALU

The OpCode in the IR

During execution of MUL RA, RD, which unit performs the actual multiplication?

 

Control Unit

 

ALU

 

Stack Pointer

 

Compiler

ALU

After execution, the PC is:

 

Cleared

 

Updated to point to the next instruction

 

Loaded into the ALU

 

Ignored until the next fetch

Updated to point to the next instruction

For MUL RA, RD, the first micro-operation is:

 

IR ← M[PC]

 

MAR ← PC

 

RA ← RA * RD

 

MDR ← M[PC]

 

MAR ← PC

After MAR ← PC, the next micro-operation is:

 

IR ← MDR

 

MDR ← M[MAR]

 

PC ← PC + 1

 

RA ← RA * RD

MDR ← M[MAR]

Once instruction is in MDR, the micro-operation is:

 

MDR ← IR

 

IR ← MDR

 

RA ← RA * RD

 

PC ← MDR

IR ← MDR

Instruction decode identifies the OpCode as:

 

ADD

 

MUL

 

SUB

 

MOV

MUL

In execution, the micro-operation performed is:

 

RA ← RA + RD

 

RA ← RA – RD

 

RA ← RA * RD

 

RA ← RD

RA ← RA * RD

After multiplication, the result is:

 

Stored in MAR

 

Stored in RA

 

Stored in PC

 

Stored in MDR

Stored in RA

After execution, the PC is updated by:

 

PC ← PC – 1

 

PC ← PC + 1

 

PC ← RA

 

PC ← MAR

PC ← PC + 1

Which of the following is the correct order of instruction cycle phases?

 

Execute → Decode → Fetch

 

Fetch → Decode → Execute

 

Decode → Fetch → Execute

 

Fetch → Execute → Decode

Fetch → Decode → Execute

In Von Neumann systems, instruction and data share:

 

Same memory and same bus

 

Different memory and same bus

 

Same memory but different bus

 

Different memory and different bus

Same memory and same bus

What limits CPU performance due to the “von Neumann bottleneck”?

 

Small cache size

 

Shared bus between instruction and data memory

 

Slow ALU

 

Large number of registers

Shared bus between instruction and data memory

Which micro-operation increments PC after fetch?

 

PC ← PC – 1

 

PC ← PC + 1

 

PC ← RA + RD

 

PC ← MDR

PC ← PC + 1

The control signals during execution are primarily generated by:

 

ALU

 

Compiler

 

Timing and Control Unit

 

Flag Register

Timing and Control Unit

Stack memory operates on the principle of:

 

FIFO

 

LIFO

 

Random access

 

Sequential access

LIFO

Which is not a special-purpose register?

 

PC

 

SP

 

IR

 

RA

RA

Which of the following contains the binary representation of the instruction being executed?

 

IR

 

MDR

 

MAR

 

PC

IR

Which phase involves control signals being sent to the ALU and registers?

 

Fetch

 

Decode

 

Execute

 

None

Execute

Which is correct for the instruction MUL RA, RD?

 

RA ← RA + RD

 

RA ← RA – RD

 

RA ← RA * RD

 

RA ← RD

RA ← RA * RD

In terms of clock rate, if a CPU runs at 3 GHz, the clock cycle time is approximately:

 

3 seconds

 

0.33 ns

 

3 ns

 

33 ns

0.33 ns

Which one is a system-level software?

 

Compiler

 

Word Processor

 

Web Browser

 

Media Player

Compiler

CPI stands for:

 

Cycles Per Instruction

 

Central Processing Instruction

 

Central Performance Index

 

Cycle Program Instruction

Cycles Per Instruction

CPI measures:

 

Number of clock cycles required per instruction

 

Number of programs executed per cycle

 

Number of instructions executed per second

 

Processor frequency

Number of clock cycles required per instruction

Which factors affect CPI?

 

Instruction mix

 

All others are true

 

Compiler optimization

 

Instruction set coverage

All others are true

If a program executes 1 million instructions and takes 2 million cycles, its average CPI is:

 

0.5

 

1.0

 

2.0

 

4.0

2.0

Reducing CPI generally:

 

Slows down program execution

 

Improves program performance

 

Reduces processor frequency

 

Increases instruction count

Improves program performance

A CPI of 1 means:

 

One instruction executes per one cycle

 

One cycle executes per instruction

 

Instruction requires multiple cycles

 

Program execution is slow

One instruction executes per one cycle

CPI and CPI- average can never be:

 

Zero

 

Fractional

 

Greater than 1

 

Dependent on program type

Zero

Speedup (S) is defined as:

 

Execution time of old / Execution time of new

 

CPI of new / CPI of old

 

Clock cycles per instruction

 

None of the above

Execution time of old / Execution time of new

A speedup of 2 means:

 

Program runs twice as fast

 

Execution time doubled

 

CPI doubled

 

Program slowed down

Program runs twice as fast

If execution time improves from 10s to 2s, speedup is:

 

2

 

5

 

8

 

10

5

Speedup depends on:

 

Improvement of enhanced part

 

Fraction of execution time affected

 

Both a and b

 

None

Both a and b

If no part of the program is improved, speedup is:

 

Infinite

 

Zero

 

1

 

Undefined

1

Which law governs the maximum possible speedup?

 

Newton’s law

 

Amdahl’s Law

 

Moore’s Law

 

Gustafson’s Law

Amdahl’s Law

Scientific applications usually:

 

Are compute-intensive/CPU-bound

 

Have large dynamic instruction counts

 

Need high floating-point performance

 

All of the above

All of the above

Commercial applications are typically:

 

Data-intensive/Input-Output bound

 

Compute-intensive

 

Instruction mix invariant

 

Real-time only

Data-intensive/Input-Output bound

Real-time programs require:

 

High throughput

 

Predictable response time

 

Maximum clock rate

 

High CPI

Predictable response time

Embedded applications often:

 

Run on power-constrained devices

 

Ignore performance

 

Have unlimited memory

 

Use supercomputers

Run on power-constrained devices

Workloads in desktop applications mostly include:

 

Office productivity, browsing

 

High-performance computing

 

Real-time embedded control

 

None

Office productivity, browsing

Which application type is most sensitive to latency?

 

Interactive real-time

 

Scientific batch processing

 

Batch transaction processing

 

Compiler optimization

Interactive real-time

Benchmark programs are designed to:

 

Stress specific system features

 

Replace applications

 

Decrease CPI

 

Avoid performance comparison

Stress specific system features

Database applications are mainly:

 

I/O bound

 

CPU bound

 

Floating-point bound

 

Cache independent

I/O bound

CPU time = ?

 

Instruction count × CPI × Clock cycle time

 

CPI ÷ Instruction count

 

Instruction count × Clock rate

 

CPI × Clock rate

Instruction count × CPI × Clock cycle time

Instruction count depends on:

 

Program

 

Compiler

 

Instruction set architecture

 

All of the above

All of the above

Clock cycle time is inverse of:

 

CPI

 

Clock frequency

 

Instruction count

 

Speedup

Clock frequency

MIPS stands for:

 

Million Instructions Per Second

 

Memory Instruction Processing System

 

Maximum Integer Processing Speed

 

Million Integer Per Second

Million Instructions Per Second

MFLOPS measures:

 

Integer performance

 

Floating-point performance

 

Cache performance

 

CPI

Floating-point performance

Which is the most reliable metric?

 

CPU execution time

 

MIPS

 

MFLOPS

 

CPI alone

CPU execution time

Dynamic instruction count refers to:

 

Total number of instructions executed at runtime

 

Number of instructions in program text

 

Instruction set size

 

Maximum instructions in compiler

Total number of instructions executed at runtime

Static instruction count is:

 

Total instructions written in source code

 

Total executed instructions

 

CPI

 

Clock cycle time

Total instructions written in source code

Which affects dynamic instruction count?

 

Input data

 

Control flow (branches, loops)

 

Compiler

 

All of the above

All of the above

Dynamic instruction count × CPI × Cycle time = ?

 

CPU time

 

Instruction rate

 

Speedup

 

MIPS

CPU time

Amdahl’s Law is used to calculate:

 

Maximum speedup achievable

 

Instruction count

 

CPI

 

Pipeline depth

Maximum speedup achievable

According to Amdahl’s Law, if fraction improved = 0, speedup is:

 

1

 

0

 

Infinite

 

Undefined

1

Formula for Amdahl’s Law speedup:

 

1 / ((1 - F) + (F/S))

 

F × S

 

CPI × IC × Time

 

Clock rate × CPI

1 / ((1 - F) + (F/S))

Amdahl’s Law shows diminishing returns because:

 

Unimproved portion dominates execution time

 

CPI increases

 

Clock frequency decreases

 

Instruction count reduces

Unimproved portion dominates execution time

In practical computing, Amdahl’s Law is applied to:

 

Decide whether partial improvement is worth it

 

Estimate CPI

 

Replace execution time metric

 

Ignore compiler optimizations

Decide whether partial improvement is worth it

Which group of binary digits directly corresponds to a single octal digit?

 

2 bits

 

3 bits

 

4 bits

 

8 bits

3 bits

Which group of binary digits directly corresponds to a single hexadecimal digit?

 

2 bits

 

3 bits

 

4 bits

 

8 bits

4 bits

Convert binary 101011 to octal.

 

23

 

53

 

33

 

43

53

Convert binary 1101101 to hexadecimal.

 

6D

 

5F

 

7C

 

3D

6D

Convert octal 745 to binary.

 

1110101

 

111100101

 

111101

 

100111101

111100101

Convert hexadecimal 2F to binary.

 

101111

 

111101

 

110011

 

111011

101111

Convert hexadecimal 3A to octal.

 

72

 

76

 

65

 

71

72

Convert octal 157 to hexadecimal.

 

6F

 

5F

 

7D

 

4F

6F

IEEE 754 single precision floating-point numbers use how many bits?

 

32

 

64

 

16

 

128

32

In IEEE 754 double precision, how many bits are allocated for the exponent field?

 

8

 

10

 

11

 

15

11

The bias used in IEEE 754 single-precision exponent representation is:

 

127

 

128

 

1023

 

255

127

The bias for the exponent field in IEEE 754 double precision is:

 

127

 

1023

 

2047

 

8192

1023

In IEEE 754 single precision, how many bits are used for the mantissa (fraction) field?

 

23

 

24

 

52

 

11

23

Which of the following represents the sign bit in IEEE floating-point format?

 

Mantissa

 

Fraction

 

Exponent

 

First bit

First bit

The number represented by IEEE 754 single precision is computed as:

 

(−1) ^sign ×(1.mantissa)×2 ^(exponent−bias)

 

(−1) ^sign ×(mantissa)×2 ^(exponent−bias)

 

(−1) ^sign ×(1.mantissa)×2 ^(exponent)

 

mantissa ÷ exponent

(−1) ^sign ×(1.mantissa)×2 ^(exponent−bias)

In floating-point arithmetic, overflow occurs when:

 

Result is too small to be represented

 

Result is too large to be represented

 

Division by zero occurs

 

Mantissa exceeds 1

Result is too large to be represented

Underflow in floating-point arithmetic means:

 

Exponent is too large

 

Value is too close to zero to be represented

 

Division result is infinite

 

Mantissa is negative

Value is too close to zero to be represented

Which of the following is a common result of overflow?

 

Rounding

 

Denormalized number

 

Infinity

 

Zero

Infinity

What is stored in IEEE 754 format to represent positive infinity?

 

Sign = 0, Exponent = all 1s, Mantissa = all 0s

 

Sign = 0, Exponent = all 0s, Mantissa = all 1s

 

Sign = 1, Exponent = all 0s, Mantissa = all 0s

 

Exponent = bias, Mantissa = 0

Sign = 0, Exponent = all 1s, Mantissa = all 0s

Negative infinity is represented in IEEE 754 as:

 

Sign = 0, Exponent = all 1s, Mantissa = all 0s

 

Sign = 1, Exponent = all 1s, Mantissa = all 0s

 

Sign = 0, Exponent = all 1s, Mantissa = all 1s

 

Sign = 1, Exponent = all 0s, Mantissa = all 1s

Sign = 1, Exponent = all 1s, Mantissa = all 0

Which representation is used for “Not a Number” (NaN) in IEEE 754?

 

Exponent all 0s, Mantissa all 1s

 

Exponent all 1s, Mantissa non-zero

 

Exponent all 1s, Mantissa all 0s

 

Exponent zero, Mantissa zero

Exponent all 1s, Mantissa non-zero

Normalized numbers in IEEE 754 have:

 

Exponent field all 1s

 

Hidden leading 1 in mantissa

 

Mantissa starting with 0

 

No exponent

Hidden leading 1 in mantissa