Special Registers

Program Counter (PC)

• Stores the address of the next instruction to be fetched during the Fetch-Decode-Execute cycle before being copied into the MAR.

• Afterwards it’s incremented to point to the next instruction.

• If there’s a jump or branch, the PC is updated with a new address.

• Controls the flow of program execution

Accumulator (ACC)

• Stores the overall and intermediate results of calculations carried out by the ALU.

• Temporarily stores data being processed, like values loaded from memory and inputs.

Control Unit (CU)

• Contains the clock and the decoder.

• Manages and co-ordinates the activities of the processor.

• It fetches, decodes and executes following the Fetch-Decode-Execute cycle.

• Sends control signals to other components to instruct them of their function.

• Ensures that instructions are carried out in the correct order and at the right time.

Arithmetic and Logic Unit (ALU)

• Performs arithmetic operations, logical operations and comparisons.

• Operates under the control of the CU.

Current Instruction Register (CIR)

• Stores the instruction currently being decoded and executed.

• The processor decodes the instruction stored in the CIR to determine what actions to perform next.

• The CIR keeps the instruction available throughout the decode and execute stages of the cycle.

Memory Address Register (MAR)

• Stores the address of the memory location to be read from or written by the processor, after receiving it from the PC during the Fetch-Decode-Execute cycle.

• The address in the MAR is sent to the memory unit so that the correct data or instruction can be fetched or stored.

Memory Data Register (MDR)

• Stores the actual data or instruction being transferred to or from memory.

• When the processor reads data from memory, the data at the address specified by the MAR is loaded into the MDR.

• When the processor writes data to memory, the data to be stored is placed into the MDR before being sent to memory.